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p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core 2 kb 3 v flash with 8-bit a/d converter rev. 04 17 december 2004 product data 1. general description the p89lpc915/916/917 are single-chip microcontrollers in low-cost 14-pin and 16-pin packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80c51 devices. many system level functions have been incorporated into the p89lpc915/916/917 in order to reduce component count, board space, and system cost. 2. features n 2 kb byte-erasable flash code memory organized into 256-byte sectors and 16-byte pages. single-byte erasing allows any byte(s) to be used as non-volatile data storage. n 256-byte ram data memory. n two 16-bit counter/timers. timer 0 (and timer 1 - p89lpc917) may be con?gured to toggle a port output upon timer over?ow or to become a pwm output. n 23-bit system timer that can also be used as a real-time clock. n 4-input multiplexed 8-bit a/d converter/single dac output. two analog comparators with selectable reference. n enhanced uart with fractional baud rate generator, break detect, framing error detection, automatic address detection and versatile interrupt capabilities. n spi communication port (P89LPC916). n internal rc oscillator option allows operation without external oscillator components. the rc oscillator (factory calibrated to 1 %) option is selectable and ?ne tunable. n 2.4 v to 3.6 v v dd operating range. i/o pins are 5 v tolerant (may be pulled up or driven to 5.5 v). n up to 14 i/o pins when using internal oscillator and reset options (P89LPC916, p89lpc917). 3. additional features ? 14-pin (p89lpc915) and 16-pin (P89LPC916, p89lpc917) tssop packages. ? a high performance 80c51 cpu provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 mhz. this is six times the performance of the standard 80c51 running at the same clock frequency. a lower clock frequency for the same performance results in power savings and reduced emi.
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 2 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? in-application programming (iap-lite) and byte erase allows code memory to be used for non-volatile data storage. ? serial flash in-circuit programming (icp) allows simple production coding with commercial eprom programmers. flash security bits prevent reading of sensitive application programs. ? watchdog timer with separate on-chip oscillator, requiring no external components. the watchdog prescaler is selectable from 8 values. ? low-voltage reset (brownout detect) allows a graceful system shutdown when power fails. may optionally be con?gured as an interrupt. ? idle and two different power-down reduced power modes. improved wake-up from power-down mode (a low interrupt input starts execution). typical power-down current is 1 m a (total power-down with voltage comparators disabled). ? active-low reset. on-chip power-on reset allows operation without external reset components. a reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. a software reset function is also available. ? programmable port output con?guration options: quasi-bidirectional, open drain, push-pull, input-only. ? port input pattern match detect. port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. ? led drive capability (20 ma) on all port pins. a maximum limit is speci?ed for the entire chip. ? controlled slew rate port outputs to reduce emi. outputs have approximately 10 ns minimum ramp times. ? only power and ground connections are required to operate the p89lpc915/916/917 when internal reset option is selected. ? four interrupt priority levels. ? five (P89LPC916), six (p89lpc915), or seven (p89lpc917) keypad interrupt inputs. ? second data pointer. ? schmitt trigger port inputs. ? emulation support.
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 3 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 4. ordering information 4.1 ordering options [1] please contact your local philips sales of?ce for availability of extended temperature ( - 40 c to +125 c) versions of the P89LPC916 and p89lpc917 devices. table 1: ordering information type number package name description version p89lpc915fdh tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 p89lpc915hdh tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 P89LPC916fdh tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 p89lpc917fdh tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 table 2: ordering options [1] type number temperature range frequency p89lpc915hdh - 40 c to +125 c 0 mhz to 18 mhz p89lpc915fdh - 40 cto+85 c P89LPC916fdh p89lpc917fdh
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 4 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5. block diagram fig 1. p89lpc915 block diagram. high performance accelerated 2-clock 80c51 cpu 2 kb code flash 256-byte data ram port 1 configurable i/os port 0 configurable i/os keypad interrupt programmable oscillator divider cpu clock on-chip rc oscillator internal bus power monitor (power-on reset, brownout reset) 002aaa822 uart analog comparators i 2 c p89lpc915 watchdog timer and oscillator timer 0 timer 1 real-time clock/ system timer adc1/dac1 external clock input
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 5 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 2. P89LPC916 block diagram. high performance accelerated 2-clock 80c51 cpu 2 kb code flash 256-byte data ram port 2 configurable i/os port 1 configurable i/os port 0 configurable i/os keypad interrupt programmable oscillator divider cpu clock internal bus power monitor (power-on reset, brownout reset) 002aaa823 uart analog comparators i 2 c P89LPC916 watchdog timer and oscillator timer 0 timer 1 real-time clock/ system timer spi adc1/dac1 on-chip rc oscillator external clock input
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 6 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 3. p89lpc917 block diagram. high performance accelerated 2-clock 80c51 cpu 2 kb code flash 256-byte data ram port 2 configurable i/os port 1 configurable i/os port 0 configurable i/os keypad interrupt programmable oscillator divider cpu clock internal bus power monitor (power-on reset, brownout reset) 002aaa824 uart analog comparators i 2 c p89lpc917 watchdog timer and oscillator timer 0 timer 1 real-time clock/ system timer adc1/dac1 on-chip rc oscillator external clock input clkout
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 7 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6. pinning information 6.1 pinning fig 4. p89lpc915 tssop14 pin con?guration. fig 5. P89LPC916 tssop16 pin con?guration. fig 6. p89lpc917 tssop16 pin con?guration. lpc915 cin2b/kbi1/ad10/p0.1 p0.2/cin2a/kbi2/ad11 kbi0/cmp2/p0.0 p0.3/cin1b/kbi3/ad12 rst/p1.5 p0.4/cin1a/kbi4/ad13/dac1 v ss p0.5/cmpref/kbi5/clkin int1/p1.4 v dd sda/int0/p1.3 p1.0/txd scl/t0/p1.2 p1.1/rxd 002aaa825 1 2 3 4 5 6 7 8 10 9 12 11 14 13 lpc916 cin2b/kbi1/ad10/p0.1 p0.2/cin2a/kbi2/ad11 ss/p2.4 p0.3/cin1b/kb13/ad12 rst/p1.5 p0.4/cin1a/kbi4/ad13/dac1 v ss p0.5/cmpref/kbi5/clkin miso/p2.3 v dd mosi/p2.2 p2.5/spiclk sda/int0/p1.3 p1.0/txd scl/t0/p1.2 p1.1/rxd 002aaa826 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 lpc917 cin2b/kbi1/ad10/p0.1 p0.2/cin2a/kbi2/ad11 kbi0/cmp2/p0.0 p0.3/cin1b/kb13/ad12 rst/p1.5 p0.4/cin1a/kbi4/ad13/dac1 v ss p0.5/cmpref/kbi5/clkin mosi/p2.2 v dd int1/p1.4 p0.7/t1/kbi7/clkout sda/int0/p1.3 p1.0/txd scl/t0/p1.2 p1.1/rxd 002aaa827 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 8 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6.2 pin description table 3: p89lpc915 pin description symbol pin type description p0.0 to p0.5 i/o port 0: port 0 is a 6-bit i/o port with user-con?gurable outputs. during reset port 0 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of port 0 pins as inputs and outputs depends upon the port con?guration selected. each port pin is con?gured independently. refer to section 9.12.1 port con?gurations and table 13 dc electrical characteristics for details. the keypad interrupt feature operates with port 0 pins. all pins have schmitt triggered inputs. port 0 also provides various special functions as described below: 2 i/o p0.0 port 0 bit 0. i cmp2 comparator 2 output. i kbi0 keyboard input 0. 1 i/o p0.1 port 0 bit 1. i cin2b comparator 2 positive input b. i kbi1 keyboard input 1. i ad10 a/d channel 1, input 0 14 i/o p0.2 port 0 bit 2. i cin2a comparator 2 positive input a. i kbi2 keyboard input 2. i ad11 a/d channel 1, input 1 13 i/o p0.3 port 0 bit 3. i cin1b comparator 1 positive input b. i kbi3 keyboard input 3. i ad12 a/d channel 1, input 2. 12 i/o p0.4 port 0 bit 4. i cin1a comparator 1 positive input a. i kbi4 keyboard input 4. i ad13 a/d channel 1, input 3. o dac1 digital to analog converter 1 output. 11 i/o p0.5 port 0 bit 5. i cmpref comparator reference (negative) input. i kbi5 keyboard input 5. i clkin external clock input.
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 9 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. p1.0 to p1.5 i/o (p1.2); i (p1.5) port 1: port 1 is a 6-bit i/o port with user-con?gurable outputs. during reset port 1 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of the inputs and outputs depends upon the port con?guration selected. refer to section 9.12.1 port con?gurations and table 13 dc electrical characteristics for details. p1.2 is an open drain when used as an output. p1.5 is input only. all pins have schmitt triggered inputs. port 1 also provides various special functions as described below: 9 i/o p1.0 port 1 bit 0 o txd serial port transmitter data. 8 i/o p1.1 port 1 bit 0 i rxd serial port receiver data. 7 i/o p1.2 port 1 bit 2. (open drain when used as an output.) i/o t0 timer/counter 0 external count input, over?ow output, or pwm output. i/o scl i 2 c-bus serial clock input/output. 6 i/o p1.3 port 1 bit 2. (open drain when used as an output.) i/o int0 external interrupt 0 input. i/o sda i 2 c-bus serial data input/output. 5 i/o p1.4 port 1 bit 2. i/o int1 external interrupt 1input. 3i p1.5 port 1 bit 5. (input only.) i rst external reset input during power-on or if selected via ucfg1. when functioning as a reset input a low on this pin resets the microcontroller, causing i/o ports and peripherals to take on their default states, and the processor begins execution at address 0. when using an oscillator frequency above 12 mhz, the reset input function of p1.5 must be enabled. an external circuit is required to hold the device in reset at power-up until v dd has reached its speci?ed level. when system power is removed v dd will fall below the minimum speci?ed operating voltage. when using an oscillator frequency above 12 mhz, in some applications, an external brownout detect circuit may be required to hold the device in reset when v dd falls below the minimum speci?ed operating voltage. also used during a power-on sequence to force in-system programming mode. v ss 4i ground: 0 v reference. v dd 10 i power supply: this is the power supply voltage for normal operation as well as idle and power-down modes. table 3: p89lpc915 pin description continued symbol pin type description
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 10 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 4: P89LPC916 pin description symbol pin type description p0.1 to p0.5 i/o port 0: port 0 is a 5-bit i/o port with user-con?gurable outputs. during reset port 0 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of port 0 pins as inputs and outputs depends upon the port con?guration selected. each port pin is con?gured independently. refer to section 9.12.1 port con?gurations and table 13 dc electrical characteristics for details. the keypad interrupt feature operates with port 0 pins. all pins have schmitt triggered inputs. port 0 also provides various special functions as described below: 1 i/o p0.1 port 0 bit 1. i cin2b comparator 2 positive input b. i kbi1 keyboard input 1. i ad10 a/d channel 1, input 0 16 i/o p0.2 port 0 bit 2. i cin2a comparator 2 positive input a. i kbi2 keyboard input 2. i ad11 a/d channel 1, input 1 15 i/o p0.3 port 0 bit 3. i cin1b comparator 1 positive input b. i kbi3 keyboard input 3. i ad12 a/d channel 1, input 2. 14 i/o p0.4 port 0 bit 4. i cin1a comparator 1 positive input a. i kbi4 keyboard input 4. i ad13 a/d channel 1, input 3. o dac1 digital to analog converter 1 output. 13 i/o p0.5 port 0 bit 5. i cmpref comparator reference (negative) input. i kbi5 keyboard input 5. i clkin external clock input.
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 11 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. p1.0 to p1.5 i/o (p1.2); i (p1.5) port 1: port 1 is a 5-bit i/o port with user-con?gurable outputs. during reset port 1 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of the p1.2 input and outputs depends upon the port con?guration selected. refer to section 9.12.1 port con?gurations and table 13 dc electrical characteristics for details. p1.2 is an open drain when used as an output. p1.5 is input only. all pins have schmitt triggered inputs. port 1 also provides various special functions as described below: 10 i/o p1.0 port 1 bit 0 o txd serial port transmitter data. 9 i/o p1.1 port 1 bit 0 i rxd serial port receiver data. 8 i/o p1.2 port 1 bit 2. (open drain when used as an output.) i/o t0 timer/counter 0 external count input, over?ow output, or pwm output. i/o scl i 2 c-bus serial clock input/output. 7 i/o p1.3 port 1 bit 2. (open drain when used as an output.) i/o int0 external interrupt 0 input. i/o sda i 2 c-bus serial data input/output. 3i p1.5 port 1 bit 5. (input only.) i rst external reset input during power-on or if selected via ucfg1. when functioning as a reset input a low on this pin resets the microcontroller, causing i/o ports and peripherals to take on their default states, and the processor begins execution at address 0. when using an oscillator frequency above 12 mhz, the reset input function of p1.5 must be enabled. an external circuit is required to hold the device in reset at power-up until v dd has reached its speci?ed level. when system power is removed v dd will fall below the minimum speci?ed operating voltage. when using an oscillator frequency above 12 mhz, in some applications, an external brownout detect circuit may be required to hold the device in reset when v dd falls below the minimum speci?ed operating voltage. also used during a power-on sequence to force in-system programming mode. table 4: P89LPC916 pin description continued symbol pin type description
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 12 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. p2.2 to p2.5 i/o port 2: port 2 is a 4-bit i/o port having user-con?gurable output types. during reset port 1 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of the p2 input and outputs depends upon the port con?guration selected. refer to section 9.12.1 port con?gurations and table 13 dc electrical characteristics for details. all pins have schmitt triggered inputs. port 2 also provides various special functions as described below: 6 i/o p2.2 port 2 bit 2. o mosi spi master out slave in. when con?gured as a master this pin is an output. when con?gured as a slave, this pin is an input. 5 i/o p2.3 port 2 bit 3. i miso spi master in slave out. when con?gured as a master this pin is an input. when con?gured as a slave, this pin is an output. 2 i/o p2.4 port 2 bit 4. i/o ss spi slave select. 11 i/o p2.5 port 2 bit 5. i/o spiclk when con?gured as a master this pin is an output. when con?gured as a slave, this pin is an input. v ss 4i ground: 0 v reference. v dd 12 i power supply: this is the power supply voltage for normal operation as well as idle and power-down modes. table 4: P89LPC916 pin description continued symbol pin type description
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 13 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 5: p89lpc917 pin description symbol pin type description p0.0 to p0.5 i/o port 0: port 0 is a 7-bit i/o port with user-con?gurable outputs. during reset port 0 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of port 0 pins as inputs and outputs depends upon the port con?guration selected. each port pin is con?gured independently. refer to section 9.12.1 port con?gurations and table 13 dc electrical characteristics for details. the keypad interrupt feature operates with port 0 pins. all pins have schmitt triggered inputs. port 0 also provides various special functions as described below: 2 i/o p0.0 port 0 bit 0. i cmp2 comparator 2 output. i kbi0 keyboard input 0. 1 i/o p0.1 port 0 bit 1. i cin2b comparator 2 positive input b. i kbi1 keyboard input 1. i ad10 a/d channel 1, input 0 16 i/o p0.2 port 0 bit 2. i cin2a comparator 2 positive input a. i kbi2 keyboard input 2. i ad11 a/d channel 1, input 1 15 i/o p0.3 port 0 bit 3. i cin1b comparator 1 positive input b. i kbi3 keyboard input 3. i ad12 a/d channel 1, input 2. 14 i/o p0.4 port 0 bit 4. i cin1a comparator 1 positive input a. i kbi4 keyboard input 4. i ad13 a/d channel 1, input 3. o dac1 digital to analog converter 1 output. 13 i/o p0.5 port 0 bit 5. i cmpref comparator reference (negative) input. i kbi5 keyboard input 5. i clkin external clock input. 11 i/o p0.7 port 0 bit 7. i t1 timer/counter 1 external count input, over?ow output, or pwm output. i kbi7 keyboard input 7. i clkout clock output.
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 14 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. p1.0 to p1.5 i/o (p1.2); i (p1.5) port 1: port 1 is a 6-bit i/o port with user-con?gurable outputs. during reset port 1 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of the outputs depends upon the port con?guration selected. refer to section 9.12.1 port con?gurations and table 13 dc electrical characteristics for details. p1.2 and p1.3 are open drain when used as outputs. p1.5 is input only. all pins have schmitt triggered inputs. port 1 also provides various special functions as described below: 10 i/o p1.0 port 1 bit 0. o txd serial port transmitter data. 9 i/o p1.1 port 1 bit 1. i rxd serial port receiver data. 8 i/o p1.2 port 1 bit 2. (open drain when used as an output.) i/o t0 timer/counter 0 external count input, over?ow, or pwm output. i/o scl i 2 c-bus serial clock input/output. 7 i/o p1.3 port 1 bit 3. (open drain when used as an output.) i/o int0 external interrupt 0 input. i/o sda i 2 c-bus serial data input/output. 6 i/o p1.4 port 1 bit 4. i/o int1 external interrupt 1input. 3i p1.5 port 1 bit 5. (input only.) i rst external reset input during power-on or if selected via ucfg1. when functioning as a reset input a low on this pin resets the microcontroller, causing i/o ports and peripherals to take on their default states, and the processor begins execution at address 0. when using an oscillator frequency above 12 mhz, the reset input function of p1.5 must be enabled. an external circuit is required to hold the device in reset at power-up until v dd has reached its speci?ed level. when system power is removed v dd will fall below the minimum speci?ed operating voltage. when using an oscillator frequency above 12 mhz, in some applications, an external brownout detect circuit may be required to hold the device in reset when v dd falls below the minimum speci?ed operating voltage. also used during a power-on sequence to force in-system programming mode. p2.2 5 i/o port 2: port 2.2 is a single-bit i/o port with a user-con?gurable output. during reset the port 2.2 latch is con?gured in the input only mode with the internal pull-up disabled. the operation of the output depends upon the port con?guration selected. refer to section 9.12.1 port con?gurations and table 13 dc electrical characteristics for details. this pin has a schmitt triggered input. v ss 4i ground: 0 v reference. v dd 12 i power supply: this is the power supply voltage for normal operation as well as idle and power-down modes. table 5: p89lpc917 pin description continued symbol pin type description
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 15 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7. logic symbols fig 7. p89lpc915 logic symbol. v dd v ss p89lpc915 port 0 port 1 txd rxd t0 int0 int1 rst scl sda 002aaa828 cmp2 cin2b cin2a cin1b cin1a cmpref kbi0 kbi1 kbi2 kbi3 kbi4 kbi5 ad10 ad11 ad12 ad13 dac1 clkin fig 8. P89LPC916 logic symbol. v dd v ss P89LPC916 port 0 port 1 txd rxd t0 int0 rst scl sda 002aaa829 cin2b cin2a cin1b cin1a cmpref kbi1 kbi2 kbi3 kbi4 kbi5 port 2 mosi miso ss spiclk ad10 ad11 ad12 ad13 clkin dac1 fig 9. p89lpc917 logic symbol. v dd v ss p89lpc917 port 0 port 1 txd rxd t0 int0 int1 rst scl sda 002aaa830 cmp2 cin2b cin2a cin1b cin1a cmpref t1 kbi0 kbi1 kbi2 kbi3 kbi4 kbi5 kbi7 port 2 ad10 ad11 ad12 ad13 clkin clkout dac1
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 16 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7.1 product comparison ta b l e 6 highlights the differences between these three devices. for a complete list of device features, please see section 2 features on page 1 . 8. special function registers remark: special function registers (sfrs) accesses are restricted in the following ways: ? user must not attempt to access any sfr locations not de?ned. ? accesses to any de?ned sfr locations must be strictly for the functions for the sfrs. ? sfr bits labeled -, 0 or 1 can only be written and read as follows: C - unless otherwise speci?ed, must be written with 0, but can return any value when read (even if it was written with 0). it is a reserved bit and may be used in future derivatives. C 0 must be written with 0, and will return a 0 when read. C 1 must be written with 1, and will return a 1 when read. table 6: product comparison type number comp 2 output spi t1 pwm output clkout int1 kbi p89lpc915 x - - - x 6 P89LPC916 - x - - - 5 p89lpc917 x - x x x 7
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 17 december 2004 17 of 72 table 7: p89lpc915 special function registers * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary bit address e7 e6 e5 e4 e3 e2 e1 e0 acc* accumulator e0h 00 00000000 adcon1 a/d control register 1 97h enbi1 enadci 1 tmm1 edge1 adci1 enadc1 adcs11 adcs10 00 00000000 adins a/d input select a3h adi13 adi12 adi11 adi10 - - - - 00 00000000 admoda a/d mode register a c0h bndi1 burst1 scc1 scan1 - - - - 00 00000000 admodb a/d mode register b a1h clk2 clk1 clk0 - endac1 - bsa1 - 00 000x0000 ad1bh a/d_1 boundary high register c4h ff 11111111 ad1bl a/d_1 boundary low register bch 00 00000000 ad1dat0 a/d_1 data register 0 d5h 00 00000000 ad1dat1 a/d_1 data register 1 d6h 00 00000000 ad1dat2 a/d_1 data register 2 d7h 00 00000000 ad1dat3 a/d_1 data register 3 f5h 00 00000000 auxr1 auxiliary function register a2h clklp ebrr - ent0 srst 0 - dps 00 000000x0 bit address f7 f6 f5 f4 f3 f2 f1 f0 b* b register f0h 00 00000000 brgr0 [2] baud rate generator rate low beh 00 00000000 brgr1 [2] baud rate generator rate high bfh 00 00000000 brgcon baud rate generator control bdh - - - - - - sbrgs brgen 00 [2] xxxxxx00 cmp1 comparator 1 control register ach - - ce1 cp1 cn1 - co1 cmf1 00 [1] xx000000 cmp2 comparator 2 control register adh - - ce2 cp2 cn2 oe2 co2 cmf2 00 [1] xx000000 divm cpu clock divide-by-m control 95h 00 00000000 dptr data pointer (2 bytes) dph data pointer high 83h 00 00000000 dpl data pointer low 82h 00 00000000 fmadrh program flash address high e7h - - - - - - 00 00000000 fmadrl program flash address low e6h 00 00000000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 17 december 2004 18 of 72 fmcon program flash control (read) e4h busy - - - hva hve sv oi 70 01110000 program flash control (write) fmcmd. 7 fmcmd. 6 fmcmd. 5 fmcmd. 4 fmcmd. 3 fmcmd. 2 fmcmd. 1 fmcmd. 0 fmdata program flash data e5h 00 00000000 i2adr i 2 c-bus slave address register dbh i2adr.6 i2adr.5 i2adr.4 i2adr.3 i2adr.2 i2adr.1 i2adr.0 gc 00 00000000 bit address df de dd dc db da d9 d8 i2con* i 2 c-bus control register d8h - i2en sta sto si aa - crsel 00 x00000x0 i2dat i 2 c-bus data register dah i2sclh serial clock generator/scl duty cycle register high ddh 00 00000000 i2scll serial clock generator/scl duty cycle register low dch 00 00000000 i2stat i 2 c-bus status register d9h sta.4 sta.3 sta.2 sta.1 sta.0 0 0 0 f8 11111000 bit address af ae ad ac ab aa a9 a8 ien0* interrupt enable 0 a8h ea ewdrt ebo es/esr et1 ex1 et0 ex0 00 00000000 bit address ef ee ed ec eb ea e9 e8 ien1* interrupt enable 1 e8h ead est - - - ec ekbi ei2c 00 [1] 00x00000 bit address bf be bd bc bb ba b9 b8 ip0* interrupt priority 0 b8h - pwdrt pbo ps/psr pt1 px1 pt0 px0 00 [1] x0000000 ip0h interrupt priority 0 high b7h - pwdrt h pboh psh/ psrh pt1h px1h pt0h px0h 00 [1] x0000000 bit address ff fe fd fc fb fa f9 f8 ip1* interrupt priority 1 f8h pad pst - - - pc pkbi pi2c 00 [1] 00x00000 ip1h interrupt priority 1 high f7h padh psth - - - pch pkbih pi2ch 00 [1] 00x00000 kbcon keypad control register 94h - - - - - - patn _sel kbif 00 [1] xxxxxx00 kbmask keypad interrupt mask register 86h 00 00000000 kbpatn keypad pattern register 93h ff 11111111 table 7: p89lpc915 special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 17 december 2004 19 of 72 bit address 87 86 85 84 83 82 81 80 p0* port 0 80h - - cmpref /kbi5 cin1a /kbi4 cin1b /kbi3 cin2a /kbi2 cin2b /kbi1 cmp2 /kbi0 [1] bit address 97 96 95 94 93 92 91 90 p1* port 1 90h - - rst int1 int0/ sda t0/scl rxd txd [1] p0m1 port 0 output mode 1 84h - - (p0m1.5) (p0m1.4) (p0m1.3) (p0m1.2) (p0m1.1) (p0m1.0) ff [1] 11111111 p0m2 port 0 output mode 2 85h - - (p0m2.5) (p0m2.4) (p0m2.3) (p0m2.2) (p0m2.1) (p0m2.0) 00 [1] 00000000 p1m1 port 1 output mode 1 91h - - - (p1m1.4) (p1m1.3) (p1m1.2) (p1m1.1) (p1m1.0) d3 [1] 11x1xx11 p1m2 port 1 output mode 2 92h - - - (p1m2.4) (p1m2.3) (p1m2.2) (p1m2.1) (p1m2.0) 00 [1] 00x0xx00 pcon power control register 87h smod1 smod0 bopd boi gf1 gf0 pmod1 pmod0 00 00000000 pcona power control register a b5h rtcpd - vcpd adpd i2pd - spd - 00 [1] 00000000 bit address d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00 00000000 pt0ad port 0 digital input disable f6h - - pt0ad.5 pt0ad.4 pt0ad.3 pt0ad.2 pt0ad.1 - 00 xx00000x rstsrc reset source register dfh - - bof pof r_bk r_wd r_sf r_ex [3] rtccon real-time clock control d1h rtcf rtcs1 rtcs0 - - - ertc rtcen 60 [1][6] 011xxx00 rtch real-time clock register high d2h 00 [6] 00000000 rtcl real-time clock register low d3h 00 [6] 00000000 saddr serial port address register a9h 00 00000000 saden serial port address enable b9h 00 00000000 sbuf serial port data buffer register 99h xx xxxxxxxx bit address 9f 9e 9d 9c 9b 9a 99 98 scon* serial port control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00 00000000 sstat serial port extended status register bah dbmod intlo cidis dbisel fe br oe stint 00 00000000 sp stack pointer 81h 07 00000111 tamod timer 0 and 1 auxiliary mode 8fh - - - - - - - t0m2 00 xxx0xxx0 bit address 8f 8e 8d 8c 8b 8a 89 88 tcon* timer 0 and 1 control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00 00000000 table 7: p89lpc915 special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 17 december 2004 20 of 72 [1] all ports are in input only (high impedance) state after power-up. [2] brgr1 and brgr0 must only be written if brgen in brgcon sfr is logic 0. if any are written while brgen = 1, the result is unpre dictable. [3] the rstsrc register re?ects the cause of the p89lpc915/916/917 reset. upon a power-up reset, all reset source ?ags are clear ed except pof and bof; the power-on reset value is xx110000. [4] after reset, the value is 111001x1, i.e., pre[2:0] are all logic 1, wdrun = 1 and wdclk = 1. wdtof bit is logic 1 after watchdog reset and is logic 0 after power-on reset. other resets will not affect wdtof. [5] on power-on reset, the trim sfr is initialized with a factory preprogrammed value. other resets will not cause initializatio n of the trim register. [6] the only reset source that affects these sfrs is power-on reset th0 timer 0 high 8ch 00 00000000 th1 timer 1 high 8dh 00 00000000 tl0 timer 0 low 8ah 00 00000000 tl1 timer 1 low 8bh 00 00000000 tmod timer 0 and 1 mode 89h t1gate t1c/t t1m1 t1m0 t0gate t0c/t t0m1 t0m0 00 00000000 trim internal oscillator trim register 96h rcclk - trim.5 trim.4 trim.3 trim.2 trim.1 trim.0 [5] [6] wdcon watchdog control register a7h pre2 pre1 pre0 - - wdrun wdtof wdclk [4] [6] wdl watchdog load c1h ff 11111111 wfeed1 watchdog feed 1 c2h wfeed2 watchdog feed 2 c3h table 7: p89lpc915 special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 17 december 2004 21 of 72 table 8: P89LPC916 special function registers * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary bit address e7 e6 e5 e4 e3 e2 e1 e0 acc* accumulator e0h 00 00000000 adcon1 a/d control register 1 97h enbi1 enadci 1 tmm1 edge1 adci1 enadc1 adcs11 adcs10 00 00000000 adins a/d input select a3h adi13 adi12 adi11 adi10 - - - - 00 00000000 admoda a/d mode register a c0h bndi1 burst1 scc1 scan1 - - - - 00 00000000 admodb a/d mode register b a1h clk2 clk1 clk0 - endac1 - bsa1 - 00 000x0000 ad1bh a/d_1 boundary high register c4h ff 11111111 ad1bl a/d_1 boundary low register bch 00 00000000 ad1dat0 a/d_1 data register 0 d5h 00 00000000 ad1dat1 a/d_1 data register 1 d6h 00 00000000 ad1dat2 a/d_1 data register 2 d7h 00 00000000 ad1dat3 a/d_1 data register 3 f5h 00 00000000 auxr1 auxiliary function register a2h clklp ebrr - ent0 srst 0 - dps 00 000000x0 bit address f7 f6 f5 f4 f3 f2 f1 f0 b* b register f0h 00 00000000 brgr0 [2] baud rate generator rate low beh 00 00000000 brgr1 [2] baud rate generator rate high bfh 00 00000000 brgcon baud rate generator control bdh - - - - - - sbrgs brgen 00 [2] xxxxxx00 cmp1 comparator 1 control register ach - - ce1 cp1 cn1 - co1 cmf1 00 [1] xx000000 cmp2 comparator 2 control register adh - - ce2 cp2 cn2 oe2 co2 cmf2 00 xx000000 divm cpu clock divide-by-m control 95h 00 00000000 dptr data pointer (2 bytes) dph data pointer high 83h 00 00000000 dpl data pointer low 82h 00 00000000 fmadrh program flash address high e7h - - - - - - 00 00000000 fmadrl program flash address low e6h 00 00000000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 17 december 2004 22 of 72 fmcon program flash control (read) e4h busy - - - hva hve sv oi 70 01110000 program flash control (write) fmcmd. 7 fmcmd. 6 fmcmd. 5 fmcmd. 4 fmcmd. 3 fmcmd. 2 fmcmd. 1 fmcmd. 0 fmdata program flash data e5h 00 00000000 i2adr i 2 c-bus slave address register dbh i2adr.6 i2adr.5 i2adr.4 i2adr.3 i2adr.2 i2adr.1 i2adr.0 gc 00 00000000 bit address df de dd dc db da d9 d8 i2con* i 2 c-bus control register d8h - i2en sta sto si aa - crsel 00 x00000x0 i2dat i 2 c-bus data register dah i2sclh serial clock generator/scl duty cycle register high ddh 00 00000000 i2scll serial clock generator/scl duty cycle register low dch 00 00000000 i2stat i 2 c-bus status register d9h sta.4 sta.3 sta.2 sta.1 sta.0 0 0 0 f8 11111000 bit address af ae ad ac ab aa a9 a8 ien0* interrupt enable 0 a8h ea ewdrt ebo es/esr et1 - et0 ex0 00 00000000 bit address ef ee ed ec eb ea e9 e8 ien1* interrupt enable 1 e8h ead est - - espi ec ekbi ei2c 00 [1] 00x00000 bit address bf be bd bc bb ba b9 b8 ip0* interrupt priority 0 b8h - pwdrt pbo ps/psr pt1 - pt0 px0 00 [1] x0000000 ip0h interrupt priority 0 high b7h - pwdrt h pboh psh/ psrh pt1h - pt0h px0h 00 [1] x0000000 bit address ff fe fd fc fb fa f9 f8 ip1* interrupt priority 1 f8h pad pst - - pspi pc pkbi pi2c 00 [1] 00x00000 ip1h interrupt priority 1 high f7h padh psth - - pspih pch pkbih pi2ch 00 [1] 00x00000 kbcon keypad control register 94h - - - - - - patn _sel kbif 00 [1] xxxxxx00 kbmask keypad interrupt mask register 86h 00 00000000 kbpatn keypad pattern register 93h ff 11111111 table 8: P89LPC916 special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 17 december 2004 23 of 72 bit address 87 86 85 84 83 82 81 80 p0* port 0 80h - - cmpref /kbi5 cin1a /kbi4 cin1b /kbi3 cin2a /kbi2 cin2b /kbi1 - [1] bit address 97 96 95 94 93 92 91 90 p1* port 1 90h - - rst - int0/ sda t0/scl rxd txd [1] bit address 97 96 95 94 93 92 91 90 p2* port 2 a0h - - spiclk ss miso mosi - - [1] p0m1 port 0 output mode 1 84h - - (p0m1.5) (p0m1.4) (p0m1.3) (p0m1.2) (p0m1.1) - ff [1] 11111111 p0m2 port 0 output mode 2 85h - - (p0m2.5) (p0m2.4) (p0m2.3) (p0m2.2) (p0m2.1) - 00 [1] 00000000 p1m1 port 1 output mode 1 91h - - - - (p1m1.3) (p1m1.2) (p1m1.1) (p1m1.0) d3 [1] 11x1xx11 p1m2 port 1 output mode 2 92h - - - - (p1m2.3) (p1m2.2) (p1m2.1) (p1m2.0) 00 [1] 00x0xx00 p2m1 port 2 output mode 1 a4h - - (p2m1.5) (p2m1.4) (p2m1.3) (p2m1.2) - - ff [1] 11111111 p2m2 port 2 output mode 2 a5h - - (p2m2.5) (p2m2.4) (p2m2.3) (p2m2.2) - - 00 [1] 00000000 pcon power control register 87h smod1 smod0 bopd boi gf1 gf0 pmod1 pmod0 00 00000000 pcona power control register a b5h rtcpd - vcpd adpd i2pd sppd spd - 00 [1] 00000000 bit address d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00 00000000 pt0ad port 0 digital input disable f6h - - pt0ad.5 pt0ad.4 pt0ad.3 pt0ad.2 pt0ad.1 - 00 xx00000x rstsrc reset source register dfh - - bof pof r_bk r_wd r_sf r_ex [3] rtccon real-time clock control d1h rtcf rtcs1 rtcs0 - - - ertc rtcen 60 [1][6] 011xxx00 rtch real-time clock register high d2h 00 [6] 00000000 rtcl real-time clock register low d3h 00 [6] 00000000 saddr serial port address register a9h 00 00000000 saden serial port address enable b9h 00 00000000 sbuf serial port data buffer register 99h xx xxxxxxxx bit address 9f 9e 9d 9c 9b 9a 99 98 scon* serial port control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00 00000000 sstat serial port extended status register bah dbmod intlo cidis dbisel fe br oe stint 00 00000000 table 8: P89LPC916 special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 17 december 2004 24 of 72 [1] all ports are in input only (high impedance) state after power-up. [2] brgr1 and brgr0 must only be written if brgen in brgcon sfr is logic 0. if any are written while brgen = 1, the result is unpre dictable. [3] the rstsrc register re?ects the cause of the p89lpc915/916/917 reset. upon a power-up reset, all reset source ?ags are clear ed except pof and bof; the power-on reset value is xx110000. [4] after reset, the value is 111001x1, i.e., pre[2:0] are all logic 1, wdrun = 1 and wdclk = 1. wdtof bit is logic 1 after watchdog reset and is logic 0 after power-on reset. other resets will not affect wdtof. [5] on power-on reset, the trim sfr is initialized with a factory preprogrammed value. other resets will not cause initializatio n of the trim register. [6] the only reset source that affects these sfrs is power-on reset. sp stack pointer 81h 07 00000111 spctl spi control register e2h ssig spen dord mstr cpol cpha spr1 spr0 04 00000100 spstat spi status register e1h spif wcol - - - - - - 00 00xxxxxx spdat spi data register e3h 00 00000000 tamod timer 0 and 1 auxiliary mode 8fh - - - - - - - t0m2 00 xxx0xxx0 bit address 8f 8e 8d 8c 8b 8a 89 88 tcon* timer 0 and 1 control 88h tf1 tr1 tf0 tr0 - - ie0 it0 00 00000000 th0 timer 0 high 8ch 00 00000000 th1 timer 1 high 8dh 00 00000000 tl0 timer 0 low 8ah 00 00000000 tl1 timer 1 low 8bh 00 00000000 tmod timer 0 and 1 mode 89h t1gate t1c/t t1m1 t1m0 t0gate t0c/t t0m1 t0m0 00 00000000 trim internal oscillator trim register 96h rcclk - trim.5 trim.4 trim.3 trim.2 trim.1 trim.0 [5] [6] wdcon watchdog control register a7h pre2 pre1 pre0 - - wdrun wdtof wdclk [4] [6] wdl watchdog load c1h ff 11111111 wfeed1 watchdog feed 1 c2h wfeed2 watchdog feed 2 c3h table 8: P89LPC916 special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 17 december 2004 25 of 72 table 9: p89lpc917 special function registers * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary bit address e7 e6 e5 e4 e3 e2 e1 e0 acc* accumulator e0h 00 00000000 adcon1 a/d control register 1 97h enbi1 enadci 1 tmm1 edge1 adci1 enadc1 adcs11 adcs10 00 00000000 adins a/d input select a3h adi13 adi12 adi11 adi10 - - - - 00 00000000 admoda a/d mode register a c0h bndi1 burst1 scc1 scan1 - - - - 00 00000000 admodb a/d mode register b a1h clk2 clk1 clk0 - endac1 - bsa1 - 00 000x0000 ad1bh a/d_1 boundary high register c4h ff 11111111 ad1bl a/d_1 boundary low register bch 00 00000000 ad1dat0 a/d_1 data register 0 d5h 00 00000000 ad1dat1 a/d_1 data register 1 d6h 00 00000000 ad1dat2 a/d_1 data register 2 d7h 00 00000000 ad1dat3 a/d_1 data register 3 f5h 00 00000000 auxr1 auxiliary function register a2h clklp ebrr ent1 ent0 srst 0 - dps 00 000000x0 bit address f7 f6 f5 f4 f3 f2 f1 f0 b* b register f0h 00 00000000 brgr0 [2] baud rate generator rate low beh 00 00000000 brgr1 [2] baud rate generator rate high bfh 00 00000000 brgcon baud rate generator control bdh - - - - - - sbrgs brgen 00 [2] xxxxxx00 cmp1 comparator 1 control register ach - - ce1 cp1 cn1 - co1 cmf1 00 [1] xx000000 cmp2 comparator 2 control register adh - - ce2 cp2 cn2 oe2 co2 cmf2 00 [1] xx000000 divm cpu clock divide-by-m control 95h 00 00000000 dptr data pointer (2 bytes) dph data pointer high 83h 00 00000000 dpl data pointer low 82h 00 00000000 fmadrh program flash address high e7h - - - - - - 00 00000000 fmadrl program flash address low e6h 00 00000000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 17 december 2004 26 of 72 fmcon program flash control (read) e4h busy - - - hva hve sv oi 70 01110000 program flash control (write) fmcmd. 7 fmcmd. 6 fmcmd. 5 fmcmd. 4 fmcmd. 3 fmcmd. 2 fmcmd. 1 fmcmd. 0 fmdata program flash data e5h 00 00000000 i2adr i 2 c-bus slave address register dbh i2adr.6 i2adr.5 i2adr.4 i2adr.3 i2adr.2 i2adr.1 i2adr.0 gc 00 00000000 bit address df de dd dc db da d9 d8 i2con* i 2 c-bus control register d8h - i2en sta sto si aa - crsel 00 x00000x0 i2dat i 2 c-bus data register dah i2sclh serial clock generator/scl duty cycle register high ddh 00 00000000 i2scll serial clock generator/scl duty cycle register low dch 00 00000000 i2stat i 2 c-bus status register d9h sta.4 sta.3 sta.2 sta.1 sta.0 0 0 0 f8 11111000 bit address af ae ad ac ab aa a9 a8 ien0* interrupt enable 0 a8h ea ewdrt ebo es/esr et1 ex1 et0 ex0 00 00000000 bit address ef ee ed ec eb ea e9 e8 ien1* interrupt enable 1 e8h ead est - - - ec ekbi ei2c 00 [1] 00x00000 bit address bf be bd bc bb ba b9 b8 ip0* interrupt priority 0 b8h - pwdrt pbo ps/psr pt1 px1 pt0 px0 00 [1] x0000000 ip0h interrupt priority 0 high b7h - pwdrt h pboh psh/ psrh pt1h px1h pt0h px0h 00 [1] x0000000 bit address ff fe fd fc fb fa f9 f8 ip1* interrupt priority 1 f8h pad pst - - - pc pkbi pi2c 00 [1] 00x00000 ip1h interrupt priority 1 high f7h padh psth - - - pch pkbih pi2ch 00 [1] 00x00000 kbcon keypad control register 94h - - - - - - patn _sel kbif 00 [1] xxxxxx00 kbmask keypad interrupt mask register 86h 00 00000000 kbpatn keypad pattern register 93h ff 11111111 table 9: p89lpc917 special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 17 december 2004 27 of 72 bit address 87 86 85 84 83 82 81 80 p0* port 0 80h t1/kbi7/ clkout - cmpref /kbi5 cin1a /kbi4 cin1b /kbi3 cin2a /kbi2 cin2b /kbi1 cmp2 /kbi0 [1] bit address 97 96 95 94 93 92 91 90 p1* port 1 90h - - rst int1 int0/ sda t0/scl rxd txd [1] p0m1 port 0 output mode 1 84h (p0m1.7) - (p0m1.5) (p0m1.4) (p0m1.3) (p0m1.2) (p0m1.1) (p0m1.0) ff [1] 11111111 p0m2 port 0 output mode 2 85h (p0m2.7) - (p0m2.5) (p0m2.4) (p0m2.3) (p0m2.2) (p0m2.1) (p0m2.0) 00 [1] 00000000 p1m1 port 1 output mode 1 91h - - - (p1m1.4) (p1m1.3) (p1m1.2) (p1m1.1) (p1m1.0) d3 [1] 11x1xx11 p1m2 port 1 output mode 2 92h - - - (p1m2.4) (p1m2.3) (p1m2.2) (p1m2.1) (p1m2.0) 00 [1] 00x0xx00 pcon power control register 87h smod1 smod0 bopd boi gf1 gf0 pmod1 pmod0 00 00000000 pcona power control register a b5h rtcpd - vcpd adpd i2pd - spd - 00 [1] 00000000 bit address d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00 00000000 pt0ad port 0 digital input disable f6h - - pt0ad.5 pt0ad.4 pt0ad.3 pt0ad.2 pt0ad.1 - 00 xx00000x rstsrc reset source register dfh - - bof pof r_bk r_wd r_sf r_ex [3] rtccon real-time clock control d1h rtcf rtcs1 rtcs0 - - - ertc rtcen 60 [1][6] 011xxx00 rtch real-time clock register high d2h 00 [6] 00000000 rtcl real-time clock register low d3h 00 [6] 00000000 saddr serial port address register a9h 00 00000000 saden serial port address enable b9h 00 00000000 sbuf serial port data buffer register 99h xx xxxxxxxx bit address 9f 9e 9d 9c 9b 9a 99 98 scon* serial port control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00 00000000 sstat serial port extended status register bah dbmod intlo cidis dbisel fe br oe stint 00 00000000 sp stack pointer 81h 07 00000111 tamod timer 0 and 1 auxiliary mode 8fh - - - t1m2 - - - t0m2 00 xxx0xxx0 bit address 8f 8e 8d 8c 8b 8a 89 88 tcon* timer 0 and 1 control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00 00000000 table 9: p89lpc917 special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 17 december 2004 28 of 72 [1] all ports are in input only (high impedance) state after power-up. [2] brgr1 and brgr0 must only be written if brgen in brgcon sfr is logic 0. if any are written while brgen = 1, the result is unpre dictable. [3] the rstsrc register re?ects the cause of the p89lpc915/916/917 reset. upon a power-up reset, all reset source ?ags are clear ed except pof and bof; the power-on reset value is xx110000. [4] after reset, the value is 111001x1, i.e., pre[2:0] are all logic 1, wdrun = 1 and wdclk = 1. wdtof bit is logic 1 after watchdog reset and is logic 0 after power-on reset. other resets will not affect wdtof. [5] on power-on reset, the trim sfr is initialized with a factory preprogrammed value. other resets will not cause initializatio n of the trim register. [6] the only reset source that affects these sfrs is power-on reset. th0 timer 0 high 8ch 00 00000000 th1 timer 1 high 8dh 00 00000000 tl0 timer 0 low 8ah 00 00000000 tl1 timer 1 low 8bh 00 00000000 tmod timer 0 and 1 mode 89h t1gate t1c/t t1m1 t1m0 t0gate t0c/t t0m1 t0m0 00 00000000 trim internal oscillator trim register 96h rcclk enclk trim.5 trim.4 trim.3 trim.2 trim.1 trim.0 [5] [6] wdcon watchdog control register a7h pre2 pre1 pre0 - - wdrun wdtof wdclk [4] [6] wdl watchdog load c1h ff 11111111 wfeed1 watchdog feed 1 c2h wfeed2 watchdog feed 2 c3h table 9: p89lpc917 special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 29 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9. functional description remark: please refer to the p89lpc915/916/917 users manual for a more detailed functional description. 9.1 enhanced cpu the p89lpc915/916/917 uses an enhanced 80c51 cpu which runs at 6 times the speed of standard 80c51 devices. a machine cycle consists of two cpu clock cycles, and most instructions execute in one or two machine cycles. 9.2 clocks 9.2.1 clock de?nitions the p89lpc915/916/917 device has several internal clocks as de?ned below: oscclk input to the divm clock divider. oscclk is selected from one of three clock sources (see figure 10 ) and can also be optionally divided to a slower frequency (see section 9.7 cpu clock (cclk) modi?cation: divm register ). note: f osc is de?ned as the oscclk frequency. cclk cpu clock; output of the clock divider. there are two cclk cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four cclk cycles). rcclk the internal 7.373 mhz rc oscillator output. pclk clock for the various peripheral devices and is cclk/2 9.2.2 cpu clock (oscclk) the p89lpc915/916/917 provide user-selectable oscillator options in generating the cpu clock. this allows optimization for a range of needs from high precision to lowest possible cost. these options are con?gured when the flash is programmed and include an on-chip watchdog oscillator, an on-chip rc oscillator, and an external clock input. 9.2.3 clock output (p89lpc917) the p89lpc917 supports a user selectable clock output function on the clkout pin. this allows external devices to synchronize to the p89lpc917. this output is enabled by the enclk bit in the trim register. the frequency of this clock output is 1 2 that of the cclk. if the clock output is not needed in idle mode, it may be turned off prior to entering idle, saving additional power. 9.3 on-chip rc oscillator option the p89lpc915/916/917 has a 6-bit trim register that can be used to tune the frequency of the rc oscillator. during reset, the trim value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 mhz, 1 % at room temperature. end-user applications can write to the trim register to adjust the on-chip rc oscillator to other frequencies.
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 30 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.4 watchdog oscillator option the watchdog has a separate oscillator which has a frequency of 400 khz. this oscillator can be used to save power when a high clock frequency is not needed. 9.5 external clock input option in this con?guration, the processor clock is derived from an external source driving the clkin pin. the rate may be from 0 hz up to 18 mhz. when using an oscillator frequency above 12 mhz, the reset input function of p1.5 must be enabled. an external circuit is required to hold the device in reset at power-up until v dd has reached its speci?ed level. when system power is removed v dd will fall below the minimum speci?ed operating voltage. when using an oscillator frequency above 12 mhz, in some applications, an external brownout detect circuit may be required to hold the device in reset when v dd falls below the minimum speci?ed operating voltage. 9.6 cpu clock (cclk) wake-up delay the p89lpc915/916/917 has an internal wake-up timer that delays the clock until it stabilizes. the delay is 224 oscclk cycles plus 60 to 100 m s. 9.7 cpu clock (cclk) modi?cation: divm register the oscclk frequency can be divided down up to 510 times by con?guring a dividing register, divm, to generate cclk. this feature makes it possible to temporarily run the cpu at a lower rate, reducing power consumption. by dividing the clock, the cpu can retain the ability to respond to events that would not exit idle mode by executing its normal program at a lower rate. this can also allow bypassing fig 10. block diagram of oscillator control. ? 2 002aaa831 rtc cpu wdt divm cclk oscclk xclk rcclk i 2 c pclk peripheral clock timers 1 & 0 clkin rc oscillator watchdog oscillator (7.3728 mhz) (400 khz) pclk rcclk spi (P89LPC916) rtcs1:0 adc1/dac1 uart baud rate generator clkout
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 31 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. the oscillator start-up time in cases where power-down mode would otherwise be used. the value of divm may be changed by the program at any time without interrupting code execution. 9.8 low power select the p89lpc915/916/917 are designed to run at 18 mhz (cclk) maximum. however, if cclk is 8 mhz or slower, the clklp sfr bit (auxr1.7) can be set to logic 1 to lower the power consumption further. on any reset, clklp is logic 0 allowing highest performance access. this bit can then be set in software if cclk is running at 8 mhz or slower.
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 32 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.9 a/d converter 9.9.1 general description the p89lpc915/916/917 has an 8-bit, 4-channel multiplexed successive approximation analog-to-digital converter. a block diagram of the a/d converter is shown in figure 11 . the a/d consists of a 4-input multiplexer which feeds a sample-and-hold circuit providing an input signal to one of two comparator inputs. the control logic in combination with the successive approximation register (sar) drives a digital-to-analog converter which provides the other input to the comparator. the output of the comparator is fed to the sar. fig 11. adc block diagram. + C comp dac1 sar 8 input mux control logic cclk 002aaa783
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 33 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.9.2 features ? an 8-bit, 4-channel multiplexed input, successive approximation a/d converter ? four a/d result registers ? six operating modes C fixed channel, single conversion mode C fixed channel, continuous conversion mode C auto scan, single conversion mode C auto scan, continuous conversion mode C dual channel, continuous conversion mode C single step mode ? three conversion start modes C timer triggered start C start immediately C edge triggered ? 8-bit conversion time of 3 3.9 m s at an adc clock of 3.3 mhz ? interrupt or polled operation ? boundary limits interrupt ? dac output to a port pin with high output impedance ? clock divider ? power-down mode 9.9.3 a/d operating modes fixed channel, single conversion mode: a single input channel can be selected for conversion. a single conversion will be performed and the result placed in the result register which corresponds to the selected input channel. an interrupt, if enabled, will be generated after the conversion completes. fixed channel, continuous conversion mode: a single input channel can be selected for continuous conversion. the results of the conversions will be sequentially placed in the four result registers. an interrupt, if enabled, will be generated after every four conversions. additional conversion results will again cycle through the four result registers, overwriting the previous results. continuous conversions continue until terminated by the user. auto scan, single conversion mode: any combination of the four input channels can be selected for conversion. a single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. an interrupt, if enabled, will be generated after all selected channels have been converted. if only a single channel is selected this is equivalent to single channel, single conversion mode. auto scan, continuous conversion mode: any combination of the four input channels can be selected for conversion. a conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. an interrupt, if enabled, will be generated after all selected
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 34 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. channels have been converted. the process will repeat starting with the ?rst selected channel. additional conversion results will again cycle through the four result registers, overwriting the previous results. continous conversions continue until terminated by the user. dual channel, continuous conversion mode: this is a variation of the auto scan continuous conversion mode where conversion occurs on two user-selectable inputs. the result of the conversion of the ?rst channel is placed in result register, ad1dat0. the result of the conversion of the second channel is placed in result register, ad1dat1. the ?rst channel is again converted and its result stored in ad1dat2. the second channel is again converted and its result placed in ad1dat3. an interrupt is generated, if enabled, after every set of four conversions (two conversions per channel). single step mode: this special mode allows single-stepping in an auto scan conversion mode. any combination of the four input channels can be selected for conversion. after each channel is converted, an interrupt is generated, if enabled, and the a/d waits for the next start condition. may be used with any of the start modes. 9.9.4 conversion start modes timer triggered start: an a/d conversion is started by the over?ow of timer 0. once a conversion has started, additional timer 0 triggers are ignored until the conversion has completed. the timer triggered start mode is available in all a/d operating modes. start immediately: programming this mode immediately starts a conversion. this start mode is available in all a/d operating modes. edge triggered: (p89lpc915/917) an a/d conversion is started by rising or falling edge of p1.4. once a conversion has started, additional edge triggers are ignored until the conversion has completed. the edge triggered start mode is available in all a/d operating modes.
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 35 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.9.5 boundary limits interrupt the a/d converters have both a high and low boundary limit register. after the four msbs have been converted, these four bits are compared with the four msbs of the boundary high and low registers. if the four msbs of the conversion are outside the limit an interrupt will be generated, if enabled. if the conversion result is within the limits, the boundary limits will again be compared after all 8 bits have been converted. an interrupt will be generated, if enabled, if the result is outside the boundary limits. the boundary limit may be disabled by clearing the boundary limit interrupt enable. 9.9.6 dac output to a port pin with high output impedance the a/d converters dac block can be output to a port pin. in this mode, the ad1dat3 register is used to hold the value fed to the dac. after a value has been written to ad1dat3, the dac output will appear on the channel 3 pin. 9.9.7 clock divider the a/d converter requires that its internal clock source be in the range of 500 khz to 3.3 mhz to maintain accuracy. a programmable clock divider that divides the clock from 1 to 8 is provided for this purpose. 9.9.8 power-down and idle mode in idle mode the a/d converter, if enabled, will continue to function and can cause the device to exit idle mode when the conversion is completed if the a/d interrupt is enabled. in power-down mode or total power-down mode, the a/d does not function. if the a/d is enabled, it will consume power. power can be reduced by disabling the a/d. 9.10 memory organization the various p89lpc915/916/917 memory spaces are as follows: ? data 256 bytes of internal data memory space (00h:ffh) accessed via direct or indirect addressing, using instructions other than movx and movc. all or part of the stack may be in this area. ? sfr special function registers. selected cpu registers and peripheral control and status registers, accessible only via direct addressing. ? code 64 kb of code memory space, accessed as part of program execution and via the movc instruction. the p89lpc915/916/917 has 2 kb of on-chip code memory. 9.11 interrupts the p89lpc915/916/917 uses a four priority level interrupt structure. this allows great ?exibility in controlling the handling of the many interrupt sources. the p89lpc915 and p89lpc917 support 13 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port tx, serial port rx, combined serial port rx and tx, brownout detect, watchdog/real-time clock, i2c, keyboard, comparators 1 and 2, and the a/d converter.
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 36 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. the P89LPC916supports 14 interrupt sources: external interrupt 0, timers 0 and 1, serial port tx, serial port rx, combined serial port rx and tx, brownout detect, watchdog/real-time clock, i2c, keyboard, comparators 1 and 2, spi, and the a/d converter. each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers ien0 or ien1. the ien0 register also contains a global disable bit, ea, which disables all interrupts. each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers ip0, ip0h, ip1, and ip1h. an interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. the highest priority interrupt service cannot be interrupted by any other interrupt source. if two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. if requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. this is called the arbitration ranking. note that the arbitration ranking is only used to resolve pending requests of the same priority level. 9.11.1 external interrupt inputs the p89lpc915 and p89lpc917 have two external interrupt inputs as well as the keypad interrupt function. the P89LPC916 has one external interrupt input as well as the keypad interrupt function these external interrupt inputs are identical to those present on the standard 80c51 microcontrollers. these external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit it1 or it0 in register tcon. in edge-triggered mode, if successive samples of the intn pin show a high in one cycle and a low in the next cycle, the interrupt request ?ag ien in tcon is set, causing an interrupt request. if an external interrupt is enabled when the p89lpc915/916/917 is put into power-down or idle mode, the interrupt will cause the processor to wake-up and resume operation. refer to section 9.14 power reduction modes for details.
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 37 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 12. interrupt sources, interrupt enables, and power-down wake-up sources. 002aaa833 ie0 ex0 ie1 ex1 bof ebo kbif ekbi interrupt to cpu wake-up (if in power-down) ewdrt cmf2 cmf1 ec ea (ie0.7) tf1 et1 ti & ri/ri es/esr ti est si ei2c spif espi rtcf ertc (rtccon.1) wdovf tf0 et0 enadci1 adci1 enbi1 bndi1 ead (p89lpc915/917) (P89LPC916)
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 38 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.12 i/o ports the P89LPC916 and p89lpc917 devices have three i/o ports: port 0, port 1, and port 2. the exact number of i/o pins available depends on the clock and reset options chosen, as shown in ta b l e 1 0 . [1] required for operation above 12 mhz. the p89lpc915 has 2i/o ports: port 0, and port 1. the exact number of i/o pins available depends on the reset option chosen, as shown in ta b l e 1 1 . [1] required for operation above 12 mhz. 9.12.1 port con?gurations except as listed below, every i/o pin on the p89lpc915/916/917 may be con?gured by software to one of four types on a bit-by-bit basis. these are: quasi-bidirectional (standard 80c51 port outputs), push-pull, open drain, and input-only. two con?guration registers for each port select the output type for each port pin. p1.5/ rst can only be an input and cannot be con?gured. scl/t0/p1.2 and sda/ int o/p1.3 may only be con?gured to be either input-only or open drain. 9.12.2 quasi-bidirectional output con?guration quasi-bidirectional output type can be used as both an input and output without the need to recon?gure the port. this is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the table 10: number of i/o pins available (P89LPC916, p89lpc917) clock source reset option number of i/o pins (16-pin package) rc oscillator or watchdog oscillator no external reset (except during power-up) 14 external rst pin supported 13 external clock input no external reset (except during power-up) 13 external rst pin supported [1] 12 table 11: number of i/o pins available (p89lpc915) clock source reset option number of i/o pins (14-pin package) rc oscillator or watchdog oscillator no external reset (except during power-up) 12 external rst pin supported 11 external clock input no external reset (except during power-up) 11 external rst pin supported [1] 10
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 39 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. pin is driven low, it is driven strongly and able to sink a fairly large current. these features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. the p89lpc915/916/917 is a 3 v device, but the pins are 5 v-tolerant. in quasi-bidirectional mode, if a user applies 5 v on the pin, there will be a current ?owing from the pin to v dd , causing extra power consumption. therefore, applying 5 v in quasi-bidirectional mode is discouraged. a quasi-bidirectional port pin has a schmitt triggered input that also has a glitch suppression circuit. 9.12.3 open-drain output con?guration the open-drain output con?guration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. to be used as a logic output, a port con?gured in this manner must have an external pull-up, typically a resistor tied to v dd . an open-drain port pin has a schmitt triggered input that also has a glitch suppression circuit. 9.12.4 input-only con?guration the input-only port con?guration has no output drivers. it is a schmitt triggered input that also has a glitch suppression circuit. 9.12.5 push-pull output con?guration the push-pull output con?guration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. the push-pull mode may be used when more source current is needed from a port output. a push-pull port pin has a schmitt triggered input that also has a glitch suppression circuit. 9.12.6 port 0 analog functions the p89lpc915/916/917 incorporates two analog comparators. in order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. digital outputs are disabled by putting the port output into the input-only (high impedance) mode as described in section 9.12.4 input-only con?guration . digital inputs on port 0 may be disabled through the use of the pt0ad register. on any reset, the pt0ad bits default to logic 0s to enable digital functions.
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 40 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.12.7 additional port features after power-up, all pins are in input-only mode. after power-up all i/o pins except p1.5, may be con?gured by software. ? pin p1.5 is input only. ? scl/t0/p1.2 and sda/ int o/p1.3 may only be con?gured to be either input-only or open drain. every output on the p89lpc915/916/917 has been designed to sink typical led drive current. however, there is a maximum total output current for all ports which must not be exceeded. please refer to table 13 dc electrical characteristics for detailed speci?cations. all port pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. the slew rate is factory-set to approximately 10 ns rise and fall times. 9.13 power monitoring functions the p89lpc915/916/917 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. this is accomplished with two hardware functions: power-on detect and brownout detect. 9.13.1 brownout detection the brownout detect function determines if the power supply voltage drops below a certain level. the default operation is for a brownout detection to cause a processor reset, however, it may alternatively be con?gured to generate an interrupt. brownout detection may be enabled or disabled in software. if brownout detection is enabled, the brownout condition occurs when v dd falls below the brownout trip voltage, v bo (see table 13 dc electrical characteristics ), and is negated when v dd rises above v bo . if the p89lpc915/916/917 device is to operate with a power supply that can be below 2.7 v, boe should be left in the unprogrammed state so that the device can operate at 2.4 v, otherwise continuous brownout reset may prevent the device from operating. for correct activation of brownout detect, the v dd rise and fall times must be observed. please see table 13 dc electrical characteristics for speci?cations. 9.13.2 power-on detection the power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. the pof ?ag in the rstsrc register is set to indicate an initial power-up condition. the pof ?ag will remain set until cleared by software. 9.14 power reduction modes the p89lpc915/916/917 supports three different power reduction modes. these modes are idle mode, power-down mode, and total power-down mode.
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 41 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.14.1 idle mode idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. any enabled interrupt source or reset may terminate idle mode. 9.14.2 power-down mode the power-down mode stops the oscillator in order to minimize power consumption. the p89lpc915/916/917 exits power-down mode via any reset, or certain interrupts. in power-down mode, the power supply voltage may be reduced to the ram keep-alive voltage v ram . this retains the ram contents at the point where power-down mode was entered. sfr contents are not guaranteed after v dd has been lowered to v ram , therefore it is highly recommended to wake up the processor via reset in this case. v dd must be raised to within the operating range before the power-down mode is exited. some chip functions continue to operate and draw power during power-down mode, increasing the total power used during power-down. these include: brownout detect, watchdog timer, comparators (note that comparators can be powered-down separately), and real-time clock (rtc)/system timer. the internal rc oscillator is disabled unless both the rc oscillator has been selected as the system clock and the rtc is enabled. 9.14.3 total power-down mode this is the same as power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. the internal rc oscillator is disabled unless both the rc oscillator has been selected as the system clock and the rtc is enabled. if the internal rc oscillator is used to clock the rtc during power-down, there will be high power consumption. please use an external low frequency clock to achieve low power with the real-time clock running during power-down. 9.15 reset the p1.5/ rst pin can function as either an active-low reset input or as a digital input, p1.5. the rpe (reset pin enable) bit in ucfg1, when set to logic 1, enables the external reset input function on p1.5. when cleared, p1.5 may be used as an input pin. remark: during a power-up sequence, the rpe selection is overridden and this pin will always function as a reset input. an external circuit connected to this pin should not hold this pin low during a power-on sequence as this will keep the device in reset. after power-up this input will function either as an external reset input or as a digital input as de?ned by the rpe bit. only a power-up reset will temporarily override the selection de?ned by rpe bit. other sources of reset will not override the rpe bit.
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 42 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. reset can be triggered from the following sources: ? external reset pin (during power-up or if user con?gured via ucfg1. this option must be used for an oscillator frequency above 12 mhz.) ? power-on detect ? brownout detect ? watchdog timer ? software reset ? uart break character detect reset. for every reset source, there is a ?ag in the reset register, rstsrc. the user can read this register to determine the most recent reset source. these ?ag bits can be cleared in software by writing a logic 0 to the corresponding bit. more than one ?ag bit may be set: ? during a power-on reset, both pof and bof are set but the other ?ag bits are cleared. ? for any other reset, previously set ?ag bits that have not been cleared will remain set. 9.16 timers/counters 0 and 1 the p89lpc915/916/917 devices have two general purpose counter/timers which are upward compatible with the standard 80c51 timer 0 and timer 1. an option to automatically toggle the t0 pin upon timer over?ow has been added. in addition an option to toggle the t1 pin upon over?ow has been added on the p89lpc917. in the timer function, the register is incremented every machine cycle. in the counter function, the register of timer 0 is incremented in response to a 1-to-0 transition at its external input pin. this external input is sampled once very machine cycle. timer 0 has ?ve operating modes (modes 0, 1, 2, 3, and 6). timer 1 has four operating modes (modes 0, 1, 2, and 3), except on the p89lpc917 where timer 1 also has mode 6. modes 0, 1, and 2 are the same for both timers/counters. mode 3 is different. 9.16.1 mode 0 putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. in this mode, the timer register is con?gured as a 13-bit register. mode 0 operation is the same for timer 0 and timer 1. 9.16.2 mode 1 mode 1 is the same as mode 0, except that all 16 bits of the timer register are used. 9.16.3 mode 2 mode 2 con?gures the timer register as an 8-bit counter with automatic reload. mode 2 operation is the same for timer 0 and timer 1.
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 43 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.16.4 mode 3 when timer 1 is in mode 3 it is stopped. timer 0 in mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. when timer 1 is in mode 3 it can still be used by the serial port as a baud rate generator. 9.16.5 mode 6 in this mode, the corresponding timer can be changed to a pwm with a full period of 256 timer clocks. 9.16.6 timer over?ow toggle output timer 0 (and timer 1 on the p89lpc917) can be con?gured to automatically toggle the timer output pin, tx, whenever a timer over?ow occurs. the same device pin that is used for the count input is also used for the timer toggle output. the port output will be a logic 1 prior to the ?rst timer over?ow when this mode is turned on. 9.17 real-time clock/system timer the p89lpc915/916/917 devices have a simple real-time clock that allows a user to continue running an accurate timer while the rest of the device is powered-down. the real-time clock can be a wake-up or an interrupt source. the real-time clock is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. when it reaches all logic 0s, the counter will be reloaded again and the rtcf ?ag will be set. the clock source for this counter can either be the cpu clock (cclk) or the external clock input, provided that the external clock input is not being used as the cpu clock. if the external clock input is used as the cpu clock, then the rtc will use cclk as its clock source. only power-on reset will reset the real-time clock and its associated sfrs to the default state. 9.18 uart the p89lpc915/916/917 has an enhanced uart that is compatible with the conventional 80c51 uart except that timer 2 over?ow cannot be used as a baud rate source. the p89lpc915/916/917 does include an independent baud rate generator. the baud rate can be selected from cclk (divided by a constant), timer 1 over?ow, or the independent baud rate generator. in addition to the baud rate generation, enhancements over the standard 80c51 uart include framing error detection, automatic address recognition, selectable double buffering and several interrupt options. the uart can be operated in 4 modes: shift register, 8-bit uart, 9-bit uart, and cclk/32 or cclk/16. 9.18.1 mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted or received, lsb ?rst. the baud rate is ?xed at 1 16 of the cpu clock frequency.
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 44 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.18.2 mode 1 10 bits are transmitted (through txd) or received (through rxd): a start bit (logic 0), 8 data bits (lsb ?rst), and a stop bit (logic 1). when data is received, the stop bit is stored in rb8 in special function register scon. the baud rate is variable and is determined by the timer 1 over?ow rate or the baud rate generator (described in section 9.18.5 baud rate generator and selection ). 9.18.3 mode 2 11 bits are transmitted (through txd) or received (through rxd): start bit (logic 0), 8 data bits (lsb ?rst), a programmable 9 th data bit, and a stop bit (logic 1). when data is transmitted, the 9 th data bit (tb8 in scon) can be assigned the value of logic 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. when data is received, the 9 th data bit goes into rb8 in special function register scon, while the stop bit is not saved. the baud rate is programmable to either 1 16 or 1 32 of the cclk frequency, as determined by the smod1 bit in pcon. 9.18.4 mode 3 11 bits are transmitted (through txd) or received (through rxd): a start bit (logic 0), 8 data bits (lsb ?rst), a programmable 9 th data bit, and a stop bit (logic 1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable and is determined by the timer 1 over?ow rate or the baud rate generator (described in section section 9.18.5 baud rate generator and selection ). 9.18.5 baud rate generator and selection the p89lpc915/916/917 has an independent baud rate generator. the baud rate is determined by a baud-rate preprogrammed into the brgr1 and brgr0 sfrs which together form a 16-bit baud rate divisor value that works in a similar manner as timer 1. if the baud rate generator is used, timer 1 can be used for other timing functions. the uart can use either timer 1 or the baud rate generator output (see figure 13 ). note that timer t1 is further divided by 2 if the smod1 bit (pcon.7) is cleared. the independent baud rate generator uses cclk. 9.18.6 framing error framing error is reported in the status register (sstat). in addition, if smod0 (pcon.6) is logic 1, framing errors can be made available in scon.7, respectively. if smod0 is logic 0, scon.7 is sm0. it is recommended that sm0 and sm1 (scon.7:6) are set up when smod0 is logic 0. fig 13. baud rate sources for uart (modes 1, 3). baud rate modes 1 and 3 sbrgs = 1 sbrgs = 0 smod1 = 0 smod1 = 1 ? 2 timer 1 overflow (pclk-based) baud rate generator (cclk-based) 002aaa419
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 45 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.18.7 break detect break detect is reported in the status register (sstat). a break is detected when 11 consecutive bits are sensed low. the break detect can be used to reset the device. 9.18.8 double buffering the uart has a transmit double buffer that allows buffering of the next character to be written to sbuf while the ?rst character is being transmitted. double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. double buffering can be disabled. if disabled (dbmod, i.e., ss tat. 7 = 0), the uart is compatible with the conventional 80c51 uart. if enabled, the uart allows writing to snbuf while the previous data is being shifted out. double buffering is only allowed in modes 1, 2 and 3. when operated in mode 0, double buffering must be disabled (dbmod = 0). 9.18.9 transmit interrupts with double buffering enabled (modes 1, 2 and 3) unlike the conventional uart, in double buffering mode, the tx interrupt is generated when the double buffer is ready to receive new data. 9.18.10 the 9 th bit (bit 8) in double buffering (modes 1, 2 and 3) if double buffering is disabled tb8 can be written before or after sbuf is written, as long as tb8 is updated some time before that bit is shifted out. tb8 must not be changed until the bit is shifted out, as indicated by the tx interrupt. if double buffering is enabled, tb8 must be updated before sbuf is written, as tb8 will be double-buffered together with sbuf data.
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 46 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.19 i 2 c-bus serial interface i 2 c-bus uses two wires (sda and scl) to transfer information between devices connected to the bus, and it has the following features: ? bi-directional data transfer between masters and slaves ? multi master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ? the i 2 c-bus may be used for test and diagnostic purposes. a typical i 2 c-bus con?guration is shown in figure 14 . the p89lpc915/916/917 device provides a byte-oriented i 2 c-bus interface that supports data transfers up to 400 khz. fig 14. i 2 c-bus con?guration. sda scl r p r p other device with i 2 c-bus interface other device with i 2 c-bus interface p1.3/sda p1.2/scl p89lpc915/916/917 i 2 c-bus 002aaa834
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 47 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.20 serial peripheral interface (spi - P89LPC916) the P89LPC916 provides another high-speed serial communication interfacethe spi interface. spi is a full-duplex, high-speed, synchronous communication bus with two operation modes: master mode and slave mode. up to 4.5 mbit/s can be supported in either master or 3.0 mbit/s in slave mode. it has a transfer completion flag and write collision flag protection. fig 15. i 2 c-bus serial interface block diagram. internal bus 002aaa421 address register comparator shift register 8 i2adr ack bit counter / arbitration & sync logic 8 i2dat timing & control logic serial clock generator cclk interrupt input filter output stage input filter output stage p1.3 p1.3/sda p1.2/scl p1.2 timer 1 overflow control registers & scl duty cycle registers i2con i2sclh i2scll 8 status decoder status bus status register 8 i2stat
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 48 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. the spi interface has four pins: spiclk, mosi, miso, and ss: ? spiclk, mosi and miso are typically tied together between two or more spi devices. data ?ows from master to slave on mosi (master out slave in) pin and ?ows from slave to master on miso (master in slave out) pin. the spiclk signal is output in the master mode and is input in the slave mode. if the spi system is disabled, i.e., spen (spctl.6) = 0 (reset value), these pins are con?gured for port functions. ? ss is the optional slave select pin. in a typical con?guration, an spi master asserts one of its port pins to select one spi device as the current slave. an spi slave device uses its ss pin to determine whether it is selected. typical connections are shown in figure 17 , 18 , and 19 . fig 16. spi block diagram (P89LPC916). 002aaa497 cpu clock divider by 4, 16, 64, 128 select clock logic spi control register read data buffer 8-bit shift register spi control spi status register spr1 spif wcol spr0 spi clock (master) pin control logic s m s m m s miso p2.3 mosi p2.2 spiclk p2.5 ss p2.4 spi interrupt request internal data bus ssig spen spen mstr dord mstr cpha cpol spr1 spr0 mstr spen clock
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 49 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.20.1 typical spi con?gurations fig 17. spi single master single slave con?guration. fig 18. spi single master multiple slaves con?guration. 002aaa435 master slave 8-bit shift register spi clock generator 8-bit shift register miso mosi spiclk port miso mosi spiclk ss 002aaa437 master slave 8-bit shift register spi clock generator 8-bit shift register miso mosi spiclk port port miso mosi spiclk ss slave 8-bit shift register miso mosi spiclk ss
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 50 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 19. spi dual device con?guration, where either can be a master or a slave. 002aaa499 master slave 8-bit shift register spi clock generator spi clock generator 8-bit shift register miso mosi spiclk miso mosi spiclk ss ss
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 51 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.21 analog comparators two analog comparators are provided on the p89lpc915/916/917. input and output options allow use of the comparators in a number of different con?gurations. comparator operation is such that the output is a logic 1 when the positive input is greater than the negative input (selectable from a pin or an internal reference voltage). otherwise the output is a zero. each comparator may be con?gured to cause an interrupt when the output value changes. comparator 1 may be output to a port pin. the overall connections to both comparators are shown in figure 20 . the comparators function to v dd = 2.4 v. when each comparator is ?rst enabled, the comparator output and interrupt ?ag are not guaranteed to be stable for 10 microseconds. the corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt ?ag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. 9.22 internal reference voltage an internal reference voltage generator may supply a default reference when a single comparator input pin is used. the value of the internal reference voltage, referred to as v ref , is 1.23 v 10 %. 9.23 comparator interrupt each comparator has an interrupt ?ag contained in its con?guration register. this ?ag is set whenever the comparator output changes state. the ?ag may be polled by software or may be used to generate an interrupt. the two comparators use one common interrupt vector. if both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the ?ags to determine which comparator caused the interrupt. fig 20. comparator input and output connections. comparator 1 cp1 cn1 (p0.4) cin1a (p0.3) cin1b (p0.5) cmpref v ref change detect co1 cmf1 interrupt 002aaa835 ec change detect cmf2 comparator 2 oe2 co2 cmp2 (p0.0) cp2 cn2 (p0.2) cin2a (p0.1) cin2b (p89lpc915/917)
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 52 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. possible comparator con?gurations are shown in figure 20 . 9.24 comparator and power reduction modes either or both comparators may remain enabled when power-down or idle mode is activated, but both comparators are disabled automatically in total power-down mode. if a comparator interrupt is enabled (except in total power-down mode), a change of the comparator output state will generate an interrupt and wake up the processor. if the comparator output to a pin is enabled, the pin should be con?gured in the push-pull mode in order to obtain fast switching times while in power-down mode. the reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. comparators consume power in power-down and idle modes, as well as in the normal operating mode. this fact should be taken into account when system power consumption is an issue. to minimize power consumption, the user can disable the comparators via pcona.5, or put the device in total power-down mode. 9.25 keypad interrupt (kbi) the keypad interrupt function is intended primarily to allow a single interrupt to be generated when port 0 is equal to or not equal to a certain pattern. this function can be used for bus address recognition or keypad recognition. the user can con?gure the port via sfrs for different tasks. the keypad interrupt mask register (kbmask) is used to de?ne which input pins connected to port 0 can trigger the interrupt. the keypad pattern register (kbpatn) is used to de?ne a pattern that is compared to the value of port 0. the keypad interrupt flag (kbif) in the keypad interrupt control register (kbcon) is set when the condition is matched while the keypad interrupt function is active. an interrupt will be generated if enabled. the patn_sel bit in the keypad interrupt control register (kbcon) is used to de?ne equal or not-equal for the comparison. in order to use the keypad interrupt as an original kbi function like in 87lpc76x series, the user needs to set kbpatn = 0ffh and patn_sel = 1 (not equal), then any key connected to port 0 which is enabled by the kbmask register will cause the hardware to set kbif and generate an interrupt if it has been enabled. the interrupt may be used to wake up the cpu from idle or power-down modes. this feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. in order to set the ?ag and cause an interrupt, the pattern on port 0 must be held longer than six cclks. 9.26 watchdog timer the watchdog timer causes a system reset when it under?ows as a result of a failure to feed the timer prior to the timer reaching its terminal count. it consists of a programmable 12-bit prescaler, and an 8-bit down counter. the down counter is decremented by a tap taken from the prescaler. the clock source for the prescaler is either the pclk or the nominal 400 khz watchdog oscillator. the watchdog timer
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 53 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. can only be reset by a power-on reset. when the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. figure 21 shows the watchdog timer in watchdog mode. feeding the watchdog requires a two-byte sequence. if pclk is selected as the watchdog clock and the cpu is powered-down, the watchdog is disabled. the watchdog timer has a time-out period that ranges from a few m s to a few seconds. please refer to the p89lpc915/916/917 users manual for more details. 9.27 additional features 9.27.1 software reset the srst bit in auxr1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. care should be taken when writing to auxr1 to avoid accidental software resets. 9.27.2 dual data pointers the dual data pointers (dptr) provides two different data pointers to specify the address used with certain instructions. the dps bit in the auxr1 register selects one of the two data pointers. bit 2 of auxr1 is permanently wired as a logic 0 so that the dps bit may be toggled (thereby switching data pointers) simply by incrementing the auxr1 register, without the possibility of inadvertently altering other bits in the register. 9.28 flash program memory 9.28.1 general description the p89lpc915/916/917 flash memory provides in-circuit electrical erasure and programming. the flash can be erased, read, and written as bytes. the sector and page erase functions can erase any flash sector (256 bytes) or page (16 bytes). the (1) watchdog reset can also be caused by an invalid feed sequence, or by writing to wdcon not immediately followed by a feed sequence. fig 21. watchdog timer in watchdog mode (wdte = 1). pre2 pre1 pre0 C C wdrun wdtof wdclk wdcon (a7h) control register prescaler 002aaa423 shadow register for wdcon 8-bit down counter wdl (c1h) watchdog oscillator pclk ? 32 mov wfeed1, #0a5h mov wfeed2, #05ah reset see note (1)
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 54 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. chip erase operation will erase the entire program memory. in-circuit programming using standard commercial programmers is available. in addition, in-application programming (iap-lite) and byte erase allows code memory to be used for non-volatile data storage. on-chip erase and write timing generation contribute to a user-friendly programming interface. the p89lpc915/916/917 flash reliably stores memory contents even after 100,000 erase and program cycles. the cell is designed to optimize the erase and programming mechanisms. the p89lpc915/916/917 uses v dd as the supply voltage to perform the program/erase algorithms. 9.28.2 features ? programming and erase over the full operating voltage range. ? byte-erase allowing code memory to be used for data storage. ? read/programming/erase using icp. ? any ?ash program operation in 4 ms. ? programming with industry-standard commercial programmers. ? programmable security for the code in the flash for each sector. ? more than 100,000 minimum erase/program cycles for each byte. ? 10-year minimum data retention. 9.28.3 flash organization the p89lpc915/916/917 program memory consists of eight 256- byte sectors. each sector can be further divided into sixteen 16-byte pages. in addition to sector erase, page erase, and byte erase, a 16-byte page register is included which allows from 1 to 16 bytes of a given page to be programmed at the same time, substantially reducing overall programming time. in addition, erasing and reprogramming of user-programmable con?guration bytes including ucfg1, the boot status bit, and the boot vector is supported. 9.28.4 flash programming and erasing different methods of erasing or programming of the flash are available. the flash may be programmed or erased in the end-user application (iap-lite) under control of the applications ?rmware. another option is to use the in-circuit programming (icp) mechanism. this icp system provides for programming through a serial clock- serial data interface using a commercially available eprom programmer which supports this device. this device does not provide for direct veri?cation of code memory contents. instead this device provides a 32-bit crc result on either a sector or the entire 2 kb of user code space. 9.28.5 in-circuit programming (icp) in-circuit programming is performed without removing the microcontroller from the system. the in-circuit programming facility consists of internal hardware resources to facilitate remote programming of the p89lpc915/916/917 through a two-wire serial interface. the philips in-circuit programming facility has made in-circuit programming in an embedded application, using commercially available programmers, possible with a minimum of additional expense in components and circuit board area. the icp function uses ?ve pins. only a small connector (with v dd ,
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 55 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. v ss , rst, clock, and data signals) needs to be available to interface your application to a commercial programmer in order to use this feature. additional details may be found in the p89lpc915/916/917 users manual . 9.28.6 in-application programming (iap-lite) in-application programming is performed in the application under the control of the microcontrollers ?rmware. the iap-lite facility consists of internal hardware resources to facilitate programming and erasing. the philips in-application programming lite has made in-application programming in an embedded application possible without additional components. this is accomplished through the use of four sfrs consisting of a control/status register, a data register, and two address registers. additional details may be found in the p89lpc915/916/917 users manual . 9.28.7 using ?ash as data storage the flash code memory array of this device supports individual byte erasing and programming. any byte in the code memory array may be read using the movc instruction, provided that the sector containing the byte has not been secured (a movc instruction is not allowed to read code memory contents of a secured sector). thus any byte in a non-secured sector may be used for non-volatile data storage. 9.28.8 user con?guration bytes some user-con?gurable features of the p89lpc915/916/917 must be de?ned at power-up and therefore cannot be set by the program after start of execution. these features are con?gured through the use of the flash byte ucfg1. please see the p89lpc915/916/917 users manual for additional details. 9.28.9 user sector security bytes there are eight user sector security bytes, each corresponding to one sector. please see the p89lpc915/916/917 users manual for additional details.
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 56 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10. limiting values [1] the following applies to limiting values: a) stresses above those listed under ta bl e 1 2 may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in table 13 dc electrical characteristics , table14ac characteristics and table 15 ac characteristics of this speci?cation are not implied. b) this product includes circuitry speci?cally designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. c) parameters are valid over operating temperature range unless otherwise speci?ed. all voltages are with respect to v ss unless otherwise noted. table 12: limiting values in accordance with the absolute maximum rating system (iec 60134). [1] symbol parameter conditions min max unit t amb(bias) operating bias ambient temperature - 55 +125 c t stg storage temperature range - 65 +150 c v n voltage on any pin to v ss - 0.5 +5.5 v i oh(i/o) high-level output current per i/o pin - 8 ma i ol(i/o) low-level output current per i/o pin - 20 ma i i/o(tot)(max) maximum total i/o current - 120 ma p tot(pack) total power dissipation per package based on package heat transfer, not device power consumption - 1.5 w
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 57 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11. static characteristics table 13: dc electrical characteristics v dd = 2.4 v to 3.6 v unless otherwise speci?ed. t amb = - 40 cto+85 c for industrial, - 40 c to +125 c extended, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit i dd(oper) power supply current, operating 3.6 v; 12 mhz [2] - 7 13 ma 3.6 v; 18 mhz [2] -1116ma i dd(idle) power supply current, idle mode 3.6 v; 12 mhz [2] - 3.6 4.8 ma 3.6 v; 18 mhz [2] -46ma i dd(pd) power supply current, power-down mode, voltage comparators powered-down 3.6 v, industrial [2] -4570 m a 3.6 v, extended [2] - - 150 m a i dd(tpd) power supply current, total power-down mode 3.6 v, industrial [2] - < 0.1 5 m a 3.6 v, extended [2] --50 m a (dv dd /dt) r v dd rise rate - - 2 mv/ m s (dv dd /dt) f v dd fall rate - - 50 mv/ m s v ram ram keep-alive voltage 1.5 - - v v th(hl) negative-going threshold voltage (schmitt trigger input) 0.22v dd 0.4v dd -v v th(lh) positive-going threshold voltage (schmitt trigger input) - 0.6v dd 0.7v dd v v hys hysteresis voltage - 0.2v dd -v v ol low-level output voltage, all ports i ol = 20 ma - 0.6 1.0 v i ol = 10 ma - 0.3 0.5 v i ol = 3.2 ma - 0.2 0.3 v v oh high-level output voltage, all ports i oh = - 8 ma; push-pull mode v dd - 1- - v i oh = - 3.2 ma; push-pull mode v dd - 0.7 v dd - 0.4 - v i oh = - 20 m a; quasi-bidirectional mode v dd - 0.3 v dd - 0.2 - v c ig input-ground capacitance [3] - - 15 pf i il logical 0 input current, all ports v in = 0.4 v [4] -- - 80 m a i li input leakage current, all ports v in =v il or v ih [5] -- 10 m a i tl logical 1-to-0 transition current, all ports v in = 2.0 v at v dd = 3.6 v [6][7] - 30 - - 450 m a r rst internal reset pull-up resistor 10 - 30 k w v bo brownout trip voltage with bov = 1, bopd = 0 2.4 v < v dd < 3.6 v 2.40 - 2.70 v
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 58 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] typical ratings are not guaranteed. the values listed are at room temperature, 3 v. [2] the i dd(oper) ,i dd(idle) , and i dd(pd) speci?cations are measured using an external clock with the following functions disabled: comparators, brownout detect, adc, i 2 c-bus, uart, spi, and watchdog timer. [3] pin capacitance is characterized but not tested. [4] measured with port in quasi-bidirectional mode. [5] measured with port in high-impedance mode. [6] ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups) [7] port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. thi s current is highest when v in is approximately 2 v. v ref band gap reference voltage 1.11 1.23 1.34 v tc (vref) band gap temperature coef?cient - 10 20 ppm/ c table 13: dc electrical characteristics continued v dd = 2.4 v to 3.6 v unless otherwise speci?ed. t amb = - 40 cto+85 c for industrial, - 40 c to +125 c extended, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 59 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12. dynamic characteristics table 14: ac characteristics v dd = 2.4 v to 3.6 v, unless otherwise speci?ed. t amb = - 40 cto+85 c for industrial, - 40 c to +125 c extended, unless otherwise speci?ed. [1] symbol parameter conditions variable clock f osc =12mhz unit min max min max f rcosc internal rc oscillator frequency (nominal f = 7.3728 mhz) trimmed to 1 % at t amb =25 c industrial 7.189 7.557 7.189 7.557 mhz extended 7.004 7.741 7.004 7.741 mhz f wdosc internal watchdog oscillator frequency (nominal f = 400 khz) 320 520 320 520 khz external clock input f osc oscillator frequency v dd = 2.4 v to 3.6 v 0 12 - - mhz t clcl clock cycle see figure 27 83- --ns f clkp clklp active frequency 0 8 - - mhz t chcx high time see figure 27 22 t clcl - t clcx 22 - ns t clcx low time see figure 27 22 t clcl - t chcx 22 - ns t clch rise time see figure 27 -8 -8ns t chcl fall time see figure 27 -8 -8ns glitch ?lter glitch rejection, p1.5/ rst pin - 50 - 50 ns signal acceptance, p1.5/ rst pin 125 - 125 - ns glitch rejection, any pin except p1.5/ rst - 15 - 15 ns signal acceptance, any pin except p1.5/ rst 50 - 50 - ns shift register (uart mode 0) t xlxl serial port clock cycle time see figure 26 16t clcl - 1333 - ns t qvxh output data set-up to clock rising edge see figure 26 13t clcl - 1083 - ns t xhqx output data hold after clock rising edge see figure 26 -t clcl + 20 - 103 ns t xhdx input data hold after clock rising edge see figure 26 -0 -0ns t dvxh input data valid to clock rising edge see figure 26 150 - 150 - ns
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 60 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. spi interface f spi operating frequency 2.0 mhz (slave) 0 cclk 6 0 2.0 mhz 3.0 mhz (master) - cclk 4 - - mhz t spicyc cycle time see figure 22 , 23 , 24 , 25 2.0 mhz (slave) 6 cclk - 500 - ns 3.0 mhz (master) 4 cclk - --ns t spilead enable lead time (slave) see figure 24 , 25 2.0 mhz 250 - 250 - ns t spilag enable lag time (slave) see figure 24 , 25 2.0 mhz 250 - 250 - ns t spiclkh spiclk high time see figure 22 , 23 , 24 , 25 master 2 cclk - 340 - ns slave 3 cclk - 190 - ns t spiclkl spiclk low time see figure 22 , 23 , 24 , 25 master 2 cclk - 340 - ns slave 3 cclk - 190 - ns t spidsu data set-up time (master or slave) see figure 22 , 23 , 24 , 25 100 - 100 - ns t spidh data hold time (master or slave) see figure 22 , 23 , 24 , 25 100 - 100 - ns t spia access time (slave) see figure 24 , 25 0 120 0 120 ns t spidis disable time (slave) see figure 24 , 25 2.0 mhz 0 240 - 240 ns t spidv enable to output data valid see figure 22 , 23 , 24 , 25 2.0 mhz 0 240 - 240 ns 3.0 mhz 0 167 - 167 ns t spioh output data hold time see figure 22 , 23 , 24 , 25 0- 0-ns table 14: ac characteristics continued v dd = 2.4 v to 3.6 v, unless otherwise speci?ed. t amb = - 40 cto+85 c for industrial, - 40 c to +125 c extended, unless otherwise speci?ed. [1] symbol parameter conditions variable clock f osc =12mhz unit min max min max
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 61 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] parameters are valid over operating temperature range unless otherwise speci?ed. parts are tested to 2 mhz, but are guarantee d to operate down to 0 hz. t spir rise time see figure 22 , 23 , 24 , 25 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss) - 2000 - 2000 ns t spif fall time see figure 22 , 23 , 24 , 25 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss) - 2000 - 2000 ns table 14: ac characteristics continued v dd = 2.4 v to 3.6 v, unless otherwise speci?ed. t amb = - 40 cto+85 c for industrial, - 40 c to +125 c extended, unless otherwise speci?ed. [1] symbol parameter conditions variable clock f osc =12mhz unit min max min max
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 62 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 15: ac characteristics v dd = 3.0 v to 3.6 v, unless otherwise speci?ed. t amb = - 40 cto+85 c for industrial, - 40 c to +125 c extended, unless otherwise speci?ed. [1] symbol parameter conditions variable clock f osc =18mhz unit min max min max f rcosc internal rc oscillator frequency (nominal f = 7.3728 mhz) trimmed to 1 % at t amb =25 c industrial 7.189 7.557 7.189 7.557 mhz extended 7.004 7.741 7.004 7.741 mhz f wdosc internal watchdog oscillator frequency (nominal f = 400 khz) 320 520 320 520 khz external clock input f osc oscillator frequency [1] 0 18 - - mhz t clcl clock cycle see figure 27 55- --ns f clkp clklp active frequency 0 8 - - mhz t chcx high time see figure 27 22 t clcl - t clcx 22 - ns t clcx low time see figure 27 22 t clcl - t chcx 22 - ns t clch rise time see figure 27 -5 -5ns t chcl fall time see figure 27 -5 -5ns glitch ?lter glitch rejection, p1.5/ rst pin - 50 - 50 ns signal acceptance, p1.5/ rst pin 125 - 125 - ns glitch rejection, any pin except p1.5/ rst - 15 - 15 ns signal acceptance, any pin except p1.5/ rst 50 - 50 - ns shift register (uart mode 0) t xlxl serial port clock cycle time see figure 26 16t clcl - 888 - ns t qvxh output data set-up to clock rising edge see figure 26 13t clcl - 722 - ns t xhqx output data hold after clock rising edge see figure 26 -t clcl + 20 - 103 ns t xhdx input data hold after clock rising edge see figure 26 -0 -0ns t dvxh input data valid to clock rising edge see figure 26 150 - 150 - ns spi interface f spi operating frequency 3.0 mhz (slave) 0 cclk 6 0 3 mhz 4.5 mhz (master) - cclk 4 - 4.5 mhz t spicyc cycle time see figure 22 , 23 , 24 , 25 3.0 mhz (slave) 6 cclk - 333 - ns 4.5 mhz (master) 4 cclk - 222 - ns
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 63 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. t spilead enable lead time (slave) see figure 24 , 25 3.0 mhz 250 - 250 - ns t spilag enable lag time (slave) see figure 24 , 25 3.0 mhz 250 - 250 - ns t spiclkh spiclk high time see figure 22 , 23 , 24 , 25 master 2 cclk - 111 - ns slave 3 cclk - 167 - ns t spiclkl spiclk low time see figure 22 , 23 , 24 , 25 master 2 cclk - 111 - ns slave 3 cclk - 167 - ns t spidsu data set-up time (master or slave) see figure 22 , 23 , 24 , 25 100 - 100 - ns t spidh data hold time (master or slave) see figure 22 , 23 , 24 , 25 100 - 100 - ns t spia access time (slave) see figure 24 , 25 0 80 0 80 ns t spidis disable time (slave) see figure 24 , 25 3.0 mhz 0 160 - 160 ns t spidv enable to output data valid see figure 22 , 23 , 24 , 25 3.0 mhz 0 160 - 160 ns 4.5 mhz 0 111 - 111 ns t spioh output data hold time see figure 22 , 23 , 24 , 25 0- 0-ns t spir rise time see figure 22 , 23 , 24 , 25 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss) - 2000 - 2000 ns table 15: ac characteristics continued v dd = 3.0 v to 3.6 v, unless otherwise speci?ed. t amb = - 40 cto+85 c for industrial, - 40 c to +125 c extended, unless otherwise speci?ed. [1] symbol parameter conditions variable clock f osc =18mhz unit min max min max
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 64 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] parameters are valid over operating temperature range unless otherwise speci?ed. parts are tested to 2 mhz, but are guarantee d to operate down to 0 hz. [2] when using an oscillator frequency above 12 mhz, the reset input function of p1.5 must be enabled. an external circuit is req uired to hold the device in reset at power-up until v dd has reached its speci?ed level. when system power is removed v dd will fall below the minimum speci?ed operating voltage. when using an oscillator frequency above 12 mhz, in some applications, an external brownout detect circuit may be required to hold the device in reset when v dd falls below the minimum speci?ed operating voltage. t spif fall time see figure 22 , 23 , 24 , 25 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss) - 2000 - 2000 ns table 15: ac characteristics continued v dd = 3.0 v to 3.6 v, unless otherwise speci?ed. t amb = - 40 cto+85 c for industrial, - 40 c to +125 c extended, unless otherwise speci?ed. [1] symbol parameter conditions variable clock f osc =18mhz unit min max min max fig 22. spi master timing (cpha = 0). t clcl t spiclkh t spiclkl master lsb/msb out master msb/lsb out t spidh t spidsu t spiclkl t spiclkh t spif t spioh t spidv t spir t spidv t spif t spif t spir t spir ss spiclk (cpol = 0) (output) 002aaa156 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 65 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 23. spi master timing (cpha = 1). t clcl t spiclkl t spiclkh master lsb/msb out master msb/lsb out t spidh t spidsu t spiclkh t spiclkl t spif t spioh t spidv t spidv t spir t spidv t spif t spir t spif t spir ss spiclk (cpol = 0) (output) 002aaa157 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in fig 24. spi slave timing (cpha = 0). t clcl t spiclkh t spiclkl t spilead t spiclkh t spiclkl t spilag t spidsu t spidh t spidh t spidsu t spidsu t spir t spia t spioh t spioh t spidis t spir slave msb/lsb out msb/lsb in lsb/msb in slave lsb/msb out t spidv t spioh t spidv t spir t spif t spir t spif ss spiclk (cpol = 0) (input) 002aaa158 spiclk (cpol = 1) (input) miso (output) mosi (input) not defined
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 66 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 25. spi slave timing (cpha = 1). t clcl t spiclkh t spiclkl t spilead t spiclkh t spiclkl t spilag t spidsu t spidh t spidh t spidsu t spir t spia t spioh t spidis t spir slave msb/lsb out not defined msb/lsb in lsb/msb in slave lsb/msb out t spidv t spioh t spidv t spioh t spidv t spir t spif t spir t spif ss spiclk (cpol = 0) (input) 002aaa159 spiclk (cpol = 1) (input) miso (output) mosi (input) t spidsu fig 26. shift register mode timing. 0 1234567 valid valid valid valid valid valid valid valid t xlxl 002aaa425 set ti set ri t xhqx t qvxh t xhdv t xhdx clock output data write to sbuf input data clear ri fig 27. external clock timing. t chcl t clcx t chcx t c t clch 002aaa416 0.2 v dd + 0.9 0.2 v dd - 0.1 v v dd - 0.5 v 0.45 v
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 67 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13. comparator electrical characteristics [1] this parameter is characterized, but not tested in production. table 16: comparator electrical characteristics v dd = 2.4 v to 3.6 v, unless otherwise speci?ed. t amb = - 40 cto+85 c for industrial, unless otherwise speci?ed. symbol parameter conditions min typ max unit v io offset voltage comparator inputs - - 20 mv v cr common mode range comparator inputs 0 - v dd - 0.3 v cmrr common mode rejection ratio [1] -- - 50 db response time - 250 500 ns comparator enable to output valid - - 10 m s i il input leakage current, comparator 0 < v in philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 68 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14. package outline fig 28. sot402-1 (tssop14). unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 69 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 29. sot403-1 (tssop16). unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core product data rev. 04 17 december 2004 70 of 72 9397 750 14397 ? koninklijke philips electronics n.v. 2004. all rights reserved. 15. revision history table 17: revision history rev date cpcn description 04 20041217 - product data (9397 750 14397) modi?cations: ? added extended temperature device (p89lpc915hdh). ? added 18 mhz information. 03 20040701 - preliminary data (9397 750 13522) 02 20040512 - preliminary data (9397 750 13278) 01 20040408 - preliminary data (9397 750 12986)
9397 750 14397 philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 04 17 december 2004 71 of 72 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 16. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 18. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 19. licenses level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c speci?cation de?ned by philips. this speci?cation can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2004. printed in the u.s.a. all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 17 december 2004 document order number: 9397 750 14397 contents philips semiconductors p89lpc915/916/917 8-bit microcontrollers with accelerated two-clock 80c51 core 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 product comparison . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 special function registers. . . . . . . . . . . . . . . . . . . . . 16 9 functional description . . . . . . . . . . . . . . . . . . . . . . . 29 9.1 enhanced cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2.1 clock de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2.2 cpu clock (oscclk) . . . . . . . . . . . . . . . . . . . . . . . 29 9.2.3 clock output (p89lpc917) . . . . . . . . . . . . . . . . . . . 29 9.3 on-chip rc oscillator option . . . . . . . . . . . . . . . . . . 29 9.4 watchdog oscillator option . . . . . . . . . . . . . . . . . . . . 30 9.5 external clock input option . . . . . . . . . . . . . . . . . . . . 30 9.6 cpu clock (cclk) wake-up delay. . . . . . . . . . . . . . 30 9.7 cpu clock (cclk) modi?cation: divm register . . . 30 9.8 low power select . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.9 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.9.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.9.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.9.3 a/d operating modes . . . . . . . . . . . . . . . . . . . . . . . . 33 9.9.4 conversion start modes . . . . . . . . . . . . . . . . . . . . . . 34 9.9.5 boundary limits interrupt . . . . . . . . . . . . . . . . . . . . . 35 9.9.6 dac output to a port pin with high output impedance 35 9.9.7 clock divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.9.8 power-down and idle mode . . . . . . . . . . . . . . . . . . . 35 9.10 memory organization . . . . . . . . . . . . . . . . . . . . . . . . 35 9.11 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.11.1 external interrupt inputs . . . . . . . . . . . . . . . . . . . . . . 36 9.12 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.12.1 port con?gurations . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.12.2 quasi-bidirectional output con?guration. . . . . . . . . . 38 9.12.3 open-drain output con?guration. . . . . . . . . . . . . . . . 39 9.12.4 input-only con?guration . . . . . . . . . . . . . . . . . . . . . . 39 9.12.5 push-pull output con?guration . . . . . . . . . . . . . . . . . 39 9.12.6 port 0 analog functions . . . . . . . . . . . . . . . . . . . . . . 39 9.12.7 additional port features . . . . . . . . . . . . . . . . . . . . . . 40 9.13 power monitoring functions . . . . . . . . . . . . . . . . . . . 40 9.13.1 brownout detection . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.13.2 power-on detection . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.14 power reduction modes . . . . . . . . . . . . . . . . . . . . . . 40 9.14.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.14.2 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.14.3 total power-down mode . . . . . . . . . . . . . . . . . . . . . . 41 9.15 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.16 timers/counters 0 and 1 . . . . . . . . . . . . . . . . . . . . . 42 9.16.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.16.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.16.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.16.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.16.5 mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.16.6 timer over?ow toggle output. . . . . . . . . . . . . . . . . . . 43 9.17 real-time clock/system timer. . . . . . . . . . . . . . . . . . 43 9.18 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.18.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.18.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.18.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.18.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.18.5 baud rate generator and selection . . . . . . . . . . . . . . 44 9.18.6 framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.18.7 break detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.18.8 double buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.18.9 transmit interrupts with double buffering enabled (modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . 45 9.18.10 the 9 th bit (bit 8) in double buffering (modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.19 i 2 c-bus serial interface . . . . . . . . . . . . . . . . . . . . . . . 46 9.20 serial peripheral interface (spi - P89LPC916). . . . . 47 9.20.1 typical spi con?gurations. . . . . . . . . . . . . . . . . . . . . 49 9.21 analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.22 internal reference voltage . . . . . . . . . . . . . . . . . . . . . 51 9.23 comparator interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 51 9.24 comparator and power reduction modes . . . . . . . . . 52 9.25 keypad interrupt (kbi) . . . . . . . . . . . . . . . . . . . . . . . 52 9.26 watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.27 additional features . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.27.1 software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.27.2 dual data pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.28 flash program memory. . . . . . . . . . . . . . . . . . . . . . . 53 9.28.1 general description. . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.28.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.28.3 flash organization . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.28.4 flash programming and erasing . . . . . . . . . . . . . . . . 54 9.28.5 in-circuit programming (icp). . . . . . . . . . . . . . . . . . . 54 9.28.6 in-application programming (iap-lite) . . . . . . . . . . . 55 9.28.7 using ?ash as data storage . . . . . . . . . . . . . . . . . . . 55 9.28.8 user con?guration bytes . . . . . . . . . . . . . . . . . . . . . . 55 9.28.9 user sector security bytes . . . . . . . . . . . . . . . . . . . . 55 10 limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11 static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 57 12 dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 59 13 comparator electrical characteristics . . . . . . . . . . . 67 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 16 data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 17 de?nitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 18 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 19 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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